fpgasystems / Centaur
Centaur, a framework for hybrid CPU-FPGA databases
☆25Updated 7 years ago
Related projects: ⓘ
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆41Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- Distributed Accelerator OS☆59Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆17Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆44Updated 7 years ago
- Tests for example Rocket Custom Coprocessors☆68Updated 4 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- Ethernet switch implementation written in Verilog☆38Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆74Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆55Updated 7 months ago
- Verilog Content Addressable Memory Module☆100Updated 2 years ago
- HLS for Networks-on-Chip☆27Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated last year
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆21Updated last year
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆19Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆32Updated 6 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆10Updated 6 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆35Updated 5 years ago
- ☆18Updated 3 years ago
- ☆15Updated last year
- ☆14Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 4 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆40Updated 11 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆16Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆35Updated 2 weeks ago
- SoCRocket - Core Repository☆32Updated 7 years ago