fpgasystems / caribouView external linksLinks
Caribou: Distributed Smart Storage built with FPGAs
☆68Jul 25, 2018Updated 7 years ago
Alternatives and similar repositories for caribou
Users that are interested in caribou are comparing it to the libraries listed below
Sorting:
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 8 years ago
- doppioDB - A hardware accelerated database☆51May 2, 2017Updated 8 years ago
- Distributed Accelerator OS☆63Apr 6, 2022Updated 3 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- This repo contains the Limago code☆91May 8, 2025Updated 9 months ago
- LeapIO: Efficient and Portable Virtual NVMe Storage on ARM SoCs (ASPLOS'20)☆29Oct 3, 2021Updated 4 years ago
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- Networking Template Library for Vivado HLS☆28Jul 12, 2020Updated 5 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆895Updated this week
- FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)☆33Feb 10, 2020Updated 6 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- An infrastructure for inline acceleration of network applications☆30Oct 25, 2021Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆51Apr 3, 2016Updated 9 years ago
- IRN's packet processing logic synthesized using Xilinx Vivado HLS☆23Dec 14, 2018Updated 7 years ago
- A networked FPGA key-value store written in Clash☆30Apr 1, 2024Updated last year
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 10 years ago
- Decision Trees Inference☆14Apr 25, 2018Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 2 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆134Sep 11, 2021Updated 4 years ago
- P4-14/16 Bluespec Compiler☆89Dec 26, 2017Updated 8 years ago
- Fletcher: A framework to integrate FPGA accelerators with Apache Arrow☆228Aug 11, 2025Updated 6 months ago
- ☆21Dec 9, 2018Updated 7 years ago
- Networking Overlay on PYNQ☆50Mar 5, 2019Updated 6 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 10 years ago
- ☆54Jun 22, 2022Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Python interface to PCIE☆40Apr 30, 2018Updated 7 years ago
- Verilog PCI express components☆25Jun 26, 2023Updated 2 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Oct 7, 2025Updated 4 months ago
- 100 Gbps TCP/IP stack for Vitis shells☆228Apr 23, 2024Updated last year
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Mar 3, 2025Updated 11 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Jul 10, 2019Updated 6 years ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆323Updated this week
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆14Nov 4, 2020Updated 5 years ago