ubimust / Alveo-U200-U250-U280-Mining-Operations-Mandatory-KnowledgeLinks
Ubimust LTD FPGA MINING - Xilinx Alveo U200 - What you need to achieve efficient FPGA Mining.
☆17Updated 6 years ago
Alternatives and similar repositories for Alveo-U200-U250-U280-Mining-Operations-Mandatory-Knowledge
Users that are interested in Alveo-U200-U250-U280-Mining-Operations-Mandatory-Knowledge are comparing it to the libraries listed below
Sorting:
- OpenCL FPGA Mining on Xilinx Alveo u200 u250 u280 FPGA Cards☆32Updated 6 years ago
- ☆44Updated 4 years ago
- Example verilog / miner for crypto mining using AWS F1 instances☆30Updated 7 years ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆81Updated 7 years ago
- A fork of Ethereum miner with OpenCL-based FPGA mining support (currently Intel FPGAs).☆43Updated 4 years ago
- Run ethash opencl kernel on Xilinx's Alveo U50☆17Updated 4 years ago
- SQRL Port of ethminer☆11Updated 4 years ago
- Bitcoin miner for Xilinx FPGAs☆97Updated 12 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- Single-source shortest paths accelerated with AWS F1 FPGA☆14Updated 7 years ago
- Maetti's Fork (Ethereum) + Altera/Intel OpenCL(FPGA)☆41Updated 4 years ago
- The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.☆53Updated 6 years ago
- Various projects of SPI loader module for xilinx fpga☆33Updated 5 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆219Updated last year
- An Open Source FPGA GroestlCoin Miner☆10Updated 7 years ago
- The FCUDA CUDA-to-RTL compiler☆20Updated 9 years ago
- Mining CryptoNight Haven on the Varium C1100☆10Updated 3 years ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- FPGA referrence implementation for aion equihash 2109☆15Updated 7 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- Virtual Platform for NVDLA☆153Updated 7 years ago
- ☆19Updated 5 years ago
- VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin☆62Updated 7 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆265Updated 2 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆30Updated 7 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Updated 11 months ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- A home for Genesis2 sources.☆43Updated 3 months ago