RSPwFPGAs / virtio-fpgaLinks
A platform for emulating Virtio devices with FPGAs
☆26Updated 4 years ago
Alternatives and similar repositories for virtio-fpga
Users that are interested in virtio-fpga are comparing it to the libraries listed below
Sorting:
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- Virtio implementation in SystemVerilog☆47Updated 7 years ago
- An FPGA-based NetTLP adapter☆26Updated 5 years ago
- ☆64Updated 5 months ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆103Updated 2 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- A library for PCIe Transaction Layer☆58Updated 3 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆37Updated 6 years ago
- P4-14/16 Bluespec Compiler☆87Updated 7 years ago
- OmniXtend cache coherence protocol☆82Updated last month
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 6 months ago
- Framework for FPGA-accelerated Middlebox Development☆44Updated 2 years ago
- User Space NVMe Driver☆25Updated 9 years ago
- ☆31Updated 7 months ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆39Updated 2 years ago
- AMD OpenNIC Shell includes the HDL source files☆117Updated 6 months ago
- An open-source UCIe implementation developed at UC Berkeley.☆15Updated last year
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆27Updated 10 months ago
- Caribou: Distributed Smart Storage built with FPGAs☆67Updated 6 years ago
- Ethernet switch implementation written in Verilog☆49Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- AIA IP compliant with the RISC-V AIA spec☆42Updated 5 months ago
- Verilog PCI express components☆22Updated 2 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆96Updated last week
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆15Updated 3 years ago