A platform for emulating Virtio devices with FPGAs
☆27Mar 31, 2021Updated 5 years ago
Alternatives and similar repositories for virtio-fpga
Users that are interested in virtio-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Virtio front-end and back-end bridge, implemented with FPGA.☆29Sep 16, 2020Updated 5 years ago
- Virtio implementation in SystemVerilog☆49Jan 23, 2018Updated 8 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- Network packet parser generator☆53Sep 11, 2020Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆40Aug 5, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Programming runtime extensions for Open vSwitch with P4☆26Apr 20, 2020Updated 6 years ago
- A library for PCIe Transaction Layer☆62Apr 27, 2022Updated 4 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 9 years ago
- NVMe Controller featuring Hardware Acceleration☆110Jun 23, 2021Updated 4 years ago
- ☆12May 31, 2016Updated 10 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆45Jul 27, 2018Updated 7 years ago
- Simple program to read & write to a pci device from userspace☆334Apr 7, 2019Updated 7 years ago
- ☆34Mar 19, 2025Updated last year
- ☆25Sep 29, 2025Updated 8 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- PCI express simulation framework for Cocotb☆205Sep 8, 2025Updated 8 months ago
- The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.☆57Nov 29, 2018Updated 7 years ago
- A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark☆50Jul 10, 2021Updated 4 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 9 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other t…☆267May 22, 2026Updated last week
- ☆11Jan 8, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism☆61Feb 27, 2022Updated 4 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆41Apr 3, 2023Updated 3 years ago
- ☆65May 6, 2020Updated 6 years ago
- ☆16May 7, 2026Updated 3 weeks ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆146Mar 6, 2026Updated 2 months ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 8 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Extracting the dense depth map from plenoptic camera (Lytro)☆19Mar 19, 2018Updated 8 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆93Mar 9, 2026Updated 2 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆40Aug 26, 2016Updated 9 years ago
- Builds and parses PCIe Transport Layer Packets (TLPs)☆45Jul 21, 2022Updated 3 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆12May 6, 2026Updated 3 weeks ago
- Open source FPGA-based NIC and platform for in-network compute☆2,347Jul 5, 2024Updated last year
- ☆12Dec 27, 2022Updated 3 years ago
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆109Jun 23, 2018Updated 7 years ago
- Dockerfile with Vivado for CI☆27Apr 17, 2020Updated 6 years ago