A platform for emulating Virtio devices with FPGAs
☆29Mar 31, 2021Updated 5 years ago
Alternatives and similar repositories for virtio-fpga
Users that are interested in virtio-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Virtio front-end and back-end bridge, implemented with FPGA.☆30Sep 16, 2020Updated 6 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆56Jan 19, 2021Updated 5 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆40Aug 5, 2020Updated 6 years ago
- Network packet parser generator☆54Sep 11, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Programming runtime extensions for Open vSwitch with P4☆26Apr 20, 2020Updated 6 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- A library for PCIe Transaction Layer☆62Apr 27, 2022Updated 4 years ago
- ☆42Jun 9, 2022Updated 4 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 9 years ago
- ☆12May 31, 2016Updated 10 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆46Jul 27, 2018Updated 8 years ago
- Simple program to read & write to a pci device from userspace☆337Apr 7, 2019Updated 7 years ago
- ☆34Mar 19, 2025Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- PCI express simulation framework for Cocotb☆211Aug 25, 2026Updated last month
- Kaggle Competition, Instance Segmentation☆86Apr 18, 2019Updated 7 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- ☆25Sep 29, 2025Updated last year
- A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark☆49Jul 10, 2021Updated 5 years ago
- NVMe Controller featuring Hardware Acceleration☆121Jun 23, 2021Updated 5 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 7 years ago
- ☆11Jan 8, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆69May 6, 2020Updated 6 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆149Jun 16, 2026Updated 3 months ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 9 years ago
- Utilities for Avalon Memory Map☆11Jun 16, 2026Updated 3 months ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Extracting the dense depth map from plenoptic camera (Lytro)☆19Mar 19, 2018Updated 8 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆42Apr 3, 2023Updated 3 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆93Mar 9, 2026Updated 7 months ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆41Aug 26, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Builds and parses PCIe Transport Layer Packets (TLPs)☆45Jul 21, 2022Updated 4 years ago
- 计算机相关知识的笔记☆11Sep 20, 2022Updated 4 years ago
- ☆10Jul 18, 2024Updated 2 years ago
- 微信小程序之记事本☆11Jun 6, 2018Updated 8 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆38Oct 26, 2021Updated 4 years ago
- JINY Kernel (Jana's tINY os) : Kernel designed from ground up for superior performance on cloud.☆15Jun 24, 2020Updated 6 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year