sunzhengyuan / auto_simulateLinks
Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation
☆12Updated 5 years ago
Alternatives and similar repositories for auto_simulate
Users that are interested in auto_simulate are comparing it to the libraries listed below
Sorting:
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- ☆19Updated 2 years ago
- ☆14Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 6 years ago
- ☆12Updated 9 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- UVM examples☆11Updated 10 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- ☆25Updated 4 years ago
- Verification IP for UART protocol☆17Updated 4 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- ☆16Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- UVM candy lover testbench which uses YASA as simulation script☆16Updated 5 years ago
- ☆22Updated 4 years ago
- ☆11Updated 9 years ago
- ☆12Updated 8 years ago
- ☆36Updated 9 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- ☆14Updated 2 years ago
- UVM Clock and Reset Agent☆13Updated 7 years ago
- UVM testbench for verifying the Pulpino SoC☆13Updated 5 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- 位宽和深度可定制的异步FIFO☆13Updated last year
- ☆20Updated 2 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- General Purpose I/O agent written in UVM☆15Updated 7 years ago
- This is a code repo for previous projects in Digital Design & Verification☆17Updated 10 years ago