Alternatives and similar repositories for auto_simulate

Users that are interested in auto_simulate are comparing it to the libraries listed below

• MilanKubavat / TestbenchGenerator
  Generate SystemVerilog/UVM block level testbench setup with python script
  ☆10Updated 8 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆20Updated 3 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago
• jinz2014 / UVM
  UVM examples
  ☆11Updated 10 years ago
• rakeshgehalot / Ethernet_switch_verification
  Verification of Ethernet Switch System Verilog
  ☆11Updated 8 years ago
• vinodsake / Last-Level-Cache-Simulator
  ☆13Updated 8 years ago
• rdou / UVM-Verification-Testbench-For-SimpleBus
  ☆11Updated 9 years ago
• zhouzaixin / arm_soc
  ☆14Updated 6 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆22Updated 6 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆12Updated 4 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated 4 months ago
• zhajio1988 / uvm_candy_lover
  UVM candy lover testbench which uses YASA as simulation script
  ☆17Updated 5 years ago
• zhangzek / Clock-Domain-Crossing-Design
  Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计
  ☆12Updated 5 years ago
• Elrori / OV_camera_on_FPGA
  OV7670 (Verilog HDL)Drive for FPGA
  ☆18Updated 6 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 6 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆16Updated 3 years ago
• redchenjs / wujian100_open
  平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）
  ☆21Updated 2 years ago
• yuxuanZh / SystemVerilog
  This is a code repo for previous projects in Digital Design & Verification
  ☆17Updated 10 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆20Updated 5 years ago
• briandong / regModel
  This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
  ☆12Updated 7 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆23Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆37Updated 10 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆20Updated 5 years ago
• Akhil-Yada / Adaptive-Filter
  An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…
  ☆12Updated 6 years ago
• aignacio / ahb_lite_bus
  AHB Bus lite v3.0
  ☆16Updated 6 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago