FPGA-Research / fosLinks
FOS - FPGA Operating System
☆70Updated 4 years ago
Alternatives and similar repositories for fos
Users that are interested in fos are comparing it to the libraries listed below
Sorting:
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆71Updated 10 months ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated last week
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- A simple DDR3 memory controller☆57Updated 2 years ago
- FuseSoC standard core library☆144Updated last month
- Python interface to FPGA interchange format☆41Updated 2 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆102Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 6 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆67Updated 10 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- ☆37Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- FPGA and Digital ASIC Build System☆74Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- ideas and eda software for vlsi design☆50Updated 3 weeks ago
- Mathematical Functions in Verilog☆93Updated 4 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆62Updated last week
- Facilitates building open source tools for working with hardware description languages (HDLs)☆64Updated 5 years ago
- ☆69Updated 4 months ago
- hardware library for hwt (= ipcore repo)☆40Updated 3 weeks ago
- ☆56Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆95Updated 3 weeks ago
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- Extensible FPGA control platform☆62Updated 2 years ago