cambridgehackers / fpgamakeLinks
Generates Makefiles to synthesize, place, and route verilog using Vivado
☆97Updated 3 years ago
Alternatives and similar repositories for fpgamake
Users that are interested in fpgamake are comparing it to the libraries listed below
Sorting:
- Python tools for Vivado Projects☆72Updated 6 years ago
- Verilog wishbone components☆124Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- FuseSoC standard core library☆149Updated 6 months ago
- Yet Another RISC-V Implementation☆99Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆219Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- ☆69Updated 4 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆117Updated 2 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- ☆137Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆117Updated 4 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 9 months ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆283Updated 6 years ago
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆175Updated last year
- Fully parametrizable combinatorial parallel LFSR/CRC module☆158Updated 9 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- VHDL-2008 Support Library☆57Updated 9 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- WISHBONE SD Card Controller IP Core☆128Updated 3 years ago
- Python-based IP-XACT parser☆142Updated last year
- Altera Advanced Synthesis Cookbook 11.0☆111Updated 2 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆203Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆127Updated 6 months ago
- FPGA and Digital ASIC Build System☆80Updated 2 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆69Updated 8 years ago
- Xilinx Unisim Library in Verilog☆87Updated 5 years ago