cambridgehackers / fpgamakeLinks
Generates Makefiles to synthesize, place, and route verilog using Vivado
☆96Updated 3 years ago
Alternatives and similar repositories for fpgamake
Users that are interested in fpgamake are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆139Updated last week
- Python tools for Vivado Projects☆73Updated 6 years ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 5 months ago
- Verilog wishbone components☆115Updated last year
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆68Updated 8 months ago
- ☆79Updated last year
- ☆132Updated 5 months ago
- FPGA and Digital ASIC Build System☆74Updated 2 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Altera Advanced Synthesis Cookbook 11.0☆104Updated 2 years ago
- ☆69Updated 2 months ago
- Doxygen with verilog support☆37Updated 6 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Yet Another RISC-V Implementation☆93Updated 8 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 4 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- SpinalHDL Hardware Math Library☆86Updated 10 months ago
- Mathematical Functions in Verilog☆92Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- Vivado build system☆69Updated 5 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆53Updated last month
- A single-wire bi-directional chip-to-chip interface for FPGAs☆121Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- OSVVM Documentation☆34Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- ☆113Updated 4 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 3 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago