Alternatives and similar repositories for fpgamake:

Users that are interested in fpgamake are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆114Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆175Updated 3 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆117Updated 8 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆101Updated 3 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆110Updated last year
• Digilent / digilent-vivado-scripts
  ☆68Updated 2 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated 2 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• ldoolitt / vhd2vl
  ☆130Updated 3 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆129Updated last year
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆62Updated 8 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 8 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 2 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆63Updated 5 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆68Updated 3 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆101Updated last year
• cjdrake / AES
  Advanced Encryption Standard (AES) SystemVerilog Core
  ☆34Updated 7 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆114Updated last month
• pieter3d / simview
  ☆77Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆55Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated last month
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆78Updated last year