Alternatives and similar repositories for fpgamake

Users that are interested in fpgamake are comparing it to the libraries listed below

• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆119Updated last year
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 10 months ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆174Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated 3 weeks ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆98Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆108Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆78Updated 2 weeks ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆121Updated this week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆116Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated 2 weeks ago
• ldoolitt / vhd2vl
  ☆137Updated 10 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆282Updated 5 years ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 3 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆68Updated 8 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆114Updated 3 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 8 months ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆104Updated 6 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 10 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆216Updated 7 months ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆90Updated 7 months ago