Alternatives and similar repositories for fpgamake:

Users that are interested in fpgamake are comparing it to the libraries listed below

• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated last month
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆57Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆100Updated 3 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆171Updated 2 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆89Updated 5 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆99Updated last year
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆92Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆78Updated 5 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆207Updated 3 months ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆62Updated 8 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆109Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated this week
• Digilent / digilent-vivado-scripts
  ☆66Updated 7 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆87Updated 5 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆66Updated 2 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆116Updated 8 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆127Updated 8 months ago
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆48Updated 6 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆152Updated last year
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆46Updated 8 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆198Updated 4 months ago
• sveditor / sveditor
  SystemVerilog Development Environment
  ☆53Updated 3 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆148Updated 7 years ago