ucsdsysnet / corundumLinks
Open source FPGA-based NIC and platform for in-network compute
☆196Updated last year
Alternatives and similar repositories for corundum
Users that are interested in corundum are comparing it to the libraries listed below
Sorting:
- 100 Gbps TCP/IP stack for Vitis shells☆211Updated last year
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆127Updated 3 years ago
- PCI express simulation framework for Cocotb☆168Updated 2 months ago
- Example designs for FPGA Drive FMC☆256Updated 6 months ago
- AMD OpenNIC Project Overview☆271Updated 2 years ago
- AMD OpenNIC Shell includes the HDL source files☆117Updated 6 months ago
- This repo contains the Limago code☆86Updated 2 months ago
- VNx: Vitis Network Examples☆150Updated 11 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆283Updated 3 weeks ago
- AXI interface modules for Cocotb☆270Updated last year
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆269Updated this week
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- NVMe Controller featuring Hardware Acceleration☆90Updated 4 years ago
- Recipe for FPGA cooking☆300Updated 9 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆354Updated last year
- ☆210Updated 3 weeks ago
- SystemC/TLM-2.0 Co-simulation framework☆251Updated last month
- Ethernet switch implementation written in Verilog☆49Updated 2 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 6 months ago
- Xilinx Tcl Store☆361Updated this week
- ☆290Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆161Updated 3 weeks ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆835Updated last week
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- ☆47Updated 5 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆131Updated last year
- ☆24Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆76Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago