Alternatives and similar repositories for corundum

Users that are interested in corundum are comparing it to the libraries listed below

• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆133Updated 4 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆225Updated last year
• Xilinx / open-nic
  AMD OpenNIC Project Overview
  ☆289Updated 2 years ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆134Updated 11 months ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆181Updated 2 months ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆277Updated 10 months ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆90Updated 6 months ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆155Updated 3 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆489Updated 3 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆298Updated 2 months ago
• Xilinx / HLS_packet_processing
  ☆48Updated 5 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆99Updated 4 years ago
• lastweek / fpga_readings
  Recipe for FPGA cooking
  ☆307Updated last year
• Xilinx / Vivado-Design-Tutorials
  ☆237Updated 3 months ago
• Xilinx / XilinxBoardStore
  ☆306Updated 2 weeks ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated last week
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• fpgasystems / Coyote
  Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…
  ☆310Updated last week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆397Updated 2 months ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆77Updated 6 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆262Updated 6 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆183Updated 3 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆111Updated 2 years ago
• fpgasystems / fpga-network-stack
  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
  ☆875Updated 5 months ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆144Updated 2 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 3 months ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆50Updated 9 years ago