andrade824 / Pulse-Width-Modulation-IP
A PWM Module IP core written in Verilog, along with a firmware driver (developed for the Zynq-7000 Programmable SoC)
☆16Updated 10 years ago
Alternatives and similar repositories for Pulse-Width-Modulation-IP:
Users that are interested in Pulse-Width-Modulation-IP are comparing it to the libraries listed below
- ☆24Updated 9 years ago
- 基于Xilinx Zynq 嵌入式软硬件协同设计实战指南☆83Updated 9 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆22Updated 5 years ago
- AD7606 driver verilog☆40Updated 5 years ago
- This is a wiki and code sharing for ZYNQ☆71Updated 9 years ago
- minimal code to access ps DDR from PL☆19Updated 5 years ago
- FPGA Technology Exchange Group相关文件管理☆44Updated 3 weeks ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆12Updated 5 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13Updated 10 years ago
- ☆15Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 5 months ago
- ☆20Updated 4 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆25Updated 9 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆39Updated 8 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆70Updated 11 months ago
- USB 2.0 Device IP Core☆66Updated 7 years ago
- ☆30Updated 5 years ago
- Repository for Xilinx PCIe DMA drivers☆45Updated 7 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也 删除了一些与项目无关的东西☆33Updated 7 years ago
- Gigabit Ethernet UDP communication driver☆75Updated 5 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Updated 4 years ago
- RTL for mipi serialize and deserialize☆11Updated 7 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆54Updated 8 years ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆65Updated 3 years ago
- turbo 8051☆29Updated 7 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆19Updated 10 years ago
- Testbenches for HDL projects☆15Updated last week