A PWM Module IP core written in Verilog, along with a firmware driver (developed for the Zynq-7000 Programmable SoC)
☆17Nov 3, 2014Updated 11 years ago
Alternatives and similar repositories for Pulse-Width-Modulation-IP
Users that are interested in Pulse-Width-Modulation-IP are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Github Repo for Embedded FPGA course by Vincent Claes☆13Mar 10, 2023Updated 3 years ago
- ☆24Sep 23, 2015Updated 10 years ago
- ☆17Aug 18, 2020Updated 5 years ago
- Video player based on MPlayer/mplayer2☆11Jun 1, 2019Updated 7 years ago
- An attempt to synthesize GPS signals in FPGA logic.☆19Feb 17, 2026Updated 5 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open Source Machine Modeling Framework. X Mach Speed.☆16Mar 3, 2022Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- FOC in FPGA implementation using MATLAB Simulink VDH code generation☆16Jul 3, 2020Updated 6 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆14Nov 26, 2024Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- OV7670 Camera Module Initialize with XILINX ZYNQ Driver☆12Oct 22, 2016Updated 9 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago
- TCL scripts for FPGA (Xilinx)☆36Jul 5, 2022Updated 4 years ago
- ☆14Mar 13, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 基于Qt qwt的串口示波器☆12May 8, 2019Updated 7 years ago
- Motion detection in both software and in hardware-accelerated OpenCV☆15Dec 26, 2016Updated 9 years ago
- Operating system in Terminal written in pure C++☆21Dec 26, 2021Updated 4 years ago
- Mean-Shift (MS) Mean-Shift (MS) is widely known as one of the most basic yet powerful tracking algorithms. Mean- Shift considers feature …☆11Dec 21, 2017Updated 8 years ago
- ☆17Sep 20, 2023Updated 2 years ago
- Serial port emulation over CAN bus☆31Jul 2, 2022Updated 4 years ago
- VimL object orient programming frame and tools☆10Dec 3, 2023Updated 2 years ago
- asm330lhh platform independent driver based on Standard C language and compliant with MISRA standard☆15Apr 10, 2026Updated 3 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Jun 10, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 8 years ago
- This project explores object tracking of human and vehicle targets in the infrared using Matlab. Using the OTCBVS Benchmark Dataset Colle…☆20Mar 2, 2015Updated 11 years ago
- Aegis Implicit Mail☆15Jan 27, 2023Updated 3 years ago
- 2025年FPGA创新设计竞赛紫光选题二/开源资料分享☆16Sep 17, 2025Updated 10 months ago
- How to create a bitbake recipe for a ROS package and cross-compile it.☆11Jul 24, 2013Updated 13 years ago
- Charting serial data on to web page☆13Jun 8, 2016Updated 10 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- video stream scaler based on FPGA and verilog☆19Mar 28, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆23Apr 16, 2025Updated last year
- FUSEQuota git mirror☆11Jul 21, 2015Updated 11 years ago
- ESP8266 powered Xilinx Virtual Cable - Xilinx WiFi JTAG!☆33Aug 25, 2021Updated 4 years ago
- IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors☆46Mar 19, 2020Updated 6 years ago
- ☆11May 27, 2014Updated 12 years ago
- Verilog Repository for GIT☆36May 4, 2021Updated 5 years ago