Alternatives and similar repositories for TOE

Users that are interested in TOE are comparing it to the libraries listed below

• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆50Updated 9 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 4 months ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆56Updated 2 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆46Updated 2 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆72Updated 3 months ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆134Updated 4 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆46Updated 11 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆79Updated 6 years ago
• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆54Updated last year
• antmicro / nvme-verilog-pcie
  ☆80Updated 3 years ago
• Xilinx / HLS_packet_processing
  ☆48Updated 6 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆46Updated 11 years ago
• luinaudt / deparser
  ☆16Updated 4 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆70Updated 8 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆34Updated 6 years ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆90Updated 7 months ago
• lucasbrasilino / net2axis
  Verilog network module. Models network traffic from pcap to AXI-Stream
  ☆22Updated 4 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆30Updated 11 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆50Updated 2 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆53Updated 4 months ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆38Updated 9 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆99Updated 4 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆72Updated 7 months ago
• AmeerAbdelhadi / Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
  Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
  ☆24Updated last year
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆185Updated 3 months ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆32Updated last year
• hpb-project / BOE
  Blockchain Offload Engine
  ☆15Updated 7 years ago