Alternatives and similar repositories for Low-Cost-and-Programmable-CRC

Users that are interested in Low-Cost-and-Programmable-CRC are comparing it to the libraries listed below

• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆55Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆58Updated last week
• oprecomp / DDR4_controller
  ☆62Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆59Updated 2 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆77Updated 10 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 4 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆47Updated 3 weeks ago
• antmicro / nvme-verilog-pcie
  ☆73Updated 3 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆74Updated 11 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 6 months ago
• mcjtag / tcam
  TCAM (Ternary Content-Addressable Memory) in Verilog
  ☆53Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆59Updated 5 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆67Updated 4 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated 2 months ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆90Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆40Updated 2 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 9 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆41Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆74Updated 7 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆78Updated last year
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆44Updated 4 months ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆39Updated 2 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆68Updated last year