FelixWinterstein / Vivado-KMeansLinks
Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
☆48Updated 8 years ago
Alternatives and similar repositories for Vivado-KMeans
Users that are interested in Vivado-KMeans are comparing it to the libraries listed below
Sorting:
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- CNN accelerator☆27Updated 8 years ago
- ☆83Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 8 years ago
- ☆88Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Caffe to VHDL☆68Updated 5 years ago
- Hot & Spicy tool suite☆23Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 6 years ago
- Huffman encoding core (Vivado HLS Project)☆12Updated 6 years ago
- ☆14Updated 9 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Algorithmic C Math Library☆66Updated last month
- ☆46Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Adding PR to the PYNQ Overlay☆19Updated 8 years ago
- Networking Overlay on PYNQ☆50Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago