FelixWinterstein / Vivado-KMeansView external linksLinks
Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
☆49Aug 31, 2017Updated 8 years ago
Alternatives and similar repositories for Vivado-KMeans
Users that are interested in Vivado-KMeans are comparing it to the libraries listed below
Sorting:
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 10 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated last year
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 10 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- An infrastructure for inline acceleration of network applications☆30Oct 25, 2021Updated 4 years ago
- Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-s…☆21May 28, 2018Updated 7 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- Caffe to VHDL☆68Jun 17, 2020Updated 5 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 9 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- Support for zScale on Spartan6 FPGAs☆15Aug 3, 2015Updated 10 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 5 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- The Shang high-level synthesis framework☆120May 29, 2014Updated 11 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago
- Architect's workbench☆10May 5, 2016Updated 9 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Apr 20, 2018Updated 7 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 10 years ago
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 7 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Nov 21, 2024Updated last year
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Hardware Snappy decompressor☆11Sep 11, 2024Updated last year
- Co-processor for whole genome alignment☆13Jun 6, 2020Updated 5 years ago
- Zynq PR Management☆13Apr 20, 2016Updated 9 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Mar 16, 2018Updated 7 years ago
- Networking Template Library for Vivado HLS☆28Jul 12, 2020Updated 5 years ago
- IP prototyping in FPGA hardware☆18Aug 28, 2018Updated 7 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆29Feb 4, 2017Updated 9 years ago
- ☆11Feb 28, 2016Updated 9 years ago