FelixWinterstein / Vivado-KMeansLinks
Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
☆48Updated 7 years ago
Alternatives and similar repositories for Vivado-KMeans
Users that are interested in Vivado-KMeans are comparing it to the libraries listed below
Sorting:
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆84Updated 4 years ago
- ☆14Updated 9 years ago
- Huffman encoding core (Vivado HLS Project)☆12Updated 5 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆54Updated 7 years ago
- CNN accelerator☆27Updated 7 years ago
- Caffe to VHDL☆67Updated 4 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Algorithmic C Machine Learning Library☆23Updated 5 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆53Updated 6 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- Python FIR Filter Package for Xilinx Pynq Board☆29Updated 7 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆29Updated 7 years ago
- verilog CNN generator for FPGA