FelixWinterstein / Vivado-KMeans

Related projects ⓘ

Alternatives and complementary repositories for Vivado-KMeans

• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• Xilinx / SDSoC_Examples
  ☆82Updated 4 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• ztgao / ConvNN_FPGA_Accelerator
  ☆13Updated 8 years ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆45Updated 11 months ago
• sopynq / huffman-encoding-core
  Huffman encoding core (Vivado HLS Project)
  ☆12Updated 5 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆51Updated 6 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆26Updated 7 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆48Updated last year
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆15Updated 5 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆38Updated 4 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆53Updated 6 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆49Updated 4 years ago
• cornell-zhang / facedetect-fpga
  ☆45Updated 4 years ago
• isi-rcg / spicy
  Hot & Spicy tool suite
  ☆23Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆102Updated 6 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆39Updated 2 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆67Updated 4 months ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆27Updated last year
• DreamIP / haddoc2
  Caffe to VHDL
  ☆66Updated 4 years ago
• wbrueckner / cv2PYNQ-The-project-behind-the-library
  This project describes how the cv2PYNQ python library was built
  ☆20Updated 6 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• yunqu / dac_2018
  Design contest for DAC 2018
  ☆17Updated 6 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆46Updated 7 years ago
• valar1234 / SDAI
  An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool
  ☆15Updated 7 years ago
• tukl-msd / LSTM-PYNQ
  ☆28Updated 6 years ago