FelixWinterstein / Vivado-KMeans
Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
☆48Updated 7 years ago
Alternatives and similar repositories for Vivado-KMeans:
Users that are interested in Vivado-KMeans are comparing it to the libraries listed below
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 7 years ago
- ☆83Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- CNN accelerator☆28Updated 7 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- ☆14Updated 9 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- ☆46Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆65Updated 2 years ago
- Caffe to VHDL☆67Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆61Updated 5 years ago
- Design contest for DAC 2018☆17Updated 7 years ago
- ☆45Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆13Updated last year
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- ☆63Updated 6 years ago