Alternatives and similar repositories for Vivado-KMeans

Users that are interested in Vivado-KMeans are comparing it to the libraries listed below

• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆20Updated 7 years ago
• Xilinx / SDSoC_Examples
  ☆84Updated 4 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago
• ztgao / ConvNN_FPGA_Accelerator
  ☆14Updated 9 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• cornell-zhang / facedetect-fpga
  ☆44Updated 5 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• hipacc / hipacc-fpga
  Fork of Hipacc generating code for Vivado HLS and Altera OpenCL
  ☆24Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 7 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆53Updated 6 years ago
• yunqu / dac_2018
  Design contest for DAC 2018
  ☆17Updated 7 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year
• wbrueckner / cv2PYNQ-The-project-behind-the-library
  This project describes how the cv2PYNQ python library was built
  ☆21Updated 6 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• tukl-msd / LSTM-PYNQ
  ☆29Updated 7 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• Xilinx / PYNQ-DL
  Xilinx Deep Learning IP
  ☆92Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆69Updated 6 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• JunnanShan / AlexNet-FPGA-implementation
  This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
  ☆21Updated 7 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• sopynq / huffman-encoding-core
  Huffman encoding core (Vivado HLS Project)
  ☆12Updated 5 years ago