Alternatives and similar repositories for Vivado-KMeans

Users that are interested in Vivado-KMeans are comparing it to the libraries listed below

• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 3 years ago
• Xilinx / SDSoC_Examples
  ☆83Updated 5 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆20Updated 7 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆68Updated 5 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆28Updated 8 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆34Updated 7 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• UCLA-VAST / HT-Deflate-FPGA
  ☆15Updated 3 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 10 years ago
• sopynq / huffman-encoding-core
  Huffman encoding core (Vivado HLS Project)
  ☆12Updated 6 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆19Updated 9 years ago
• tukl-msd / LSTM-PYNQ
  ☆28Updated 7 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆32Updated 2 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆68Updated 9 years ago
• cornell-zhang / facedetect-fpga
  ☆46Updated 5 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 8 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• ztgao / ConvNN_FPGA_Accelerator
  ☆14Updated 10 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆16Updated 6 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 3 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆120Updated 11 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 4 years ago
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆54Updated 7 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆109Updated 5 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 5 years ago
• Xilinx / PYNQ-DL
  Xilinx Deep Learning IP
  ☆94Updated 4 years ago