Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
☆72Jan 29, 2017Updated 9 years ago
Alternatives and similar repositories for nfmac10g
Users that are interested in nfmac10g are comparing it to the libraries listed below
Sorting:
- ☆14May 15, 2023Updated 2 years ago
- 10 Gbit/s flexible and extensible Ethernet FPGA-based traffic generator☆11Oct 3, 2014Updated 11 years ago
- Ethernet 10GE MAC☆46Jul 17, 2014Updated 11 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Apr 3, 2023Updated 2 years ago
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- Verilog FT245 to AXI stream interface☆29Jun 20, 2018Updated 7 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆177Jan 24, 2024Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆160Jul 16, 2018Updated 7 years ago
- Verilog PCI express components☆25Jun 26, 2023Updated 2 years ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- Verilog Ethernet components for FPGA implementation☆2,865Feb 27, 2025Updated last year
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- Distributed Accelerator OS☆64Apr 6, 2022Updated 3 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Jan 8, 2019Updated 7 years ago
- UART -> AXI Bridge☆71Jul 1, 2021Updated 4 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 8 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- Verilog Ethernet Switch (layer 2)☆51Oct 18, 2023Updated 2 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆136Sep 11, 2021Updated 4 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet☆29Feb 4, 2020Updated 6 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆899Updated this week
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- SPIFlashProgrammer is a small and fast SPI Flash programming tool that's designed to be easy to use☆15May 15, 2023Updated 2 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- OpenFlow Switch Hardware Implement Code☆11Jul 1, 2015Updated 10 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 4 years ago
- Computational Storage Device based on the open source project OpenSSD.☆30Oct 25, 2020Updated 5 years ago
- ☆15Apr 18, 2023Updated 2 years ago
- TCP Offload Engine☆78Nov 18, 2017Updated 8 years ago
- Docker installation of Vivado tooling☆35Feb 10, 2026Updated 3 weeks ago