Alternatives and similar repositories for nfmac10g

Users that are interested in nfmac10g are comparing it to the libraries listed below

• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆68Updated 2 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆114Updated 3 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆125Updated 2 weeks ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆46Updated 11 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Updated 2 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆67Updated 6 months ago
• CospanDesign / nysa-sata
  ☆87Updated 8 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆182Updated 2 months ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆46Updated 10 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆51Updated last year
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆50Updated 9 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆29Updated 11 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆97Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆49Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆71Updated 2 months ago
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆60Updated 6 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 8 months ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 9 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago