Alternatives and similar repositories for Microarchitectural-attacks:

Users that are interested in Microarchitectural-attacks are comparing it to the libraries listed below

• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆30Updated last year
• nepoche / Flush-Reload
  A flush-reload side channel attack implementation
  ☆45Updated 2 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆19Updated 4 years ago
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆49Updated 5 years ago
• Miro-H / CacheSC
  Library for Prime+Probe cache side-channel attacks on L1 and L2
  ☆30Updated 4 years ago
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆14Updated 5 years ago
• Secure-AI-Systems-Group / Mastik
  GitHub (mirror) repository for the Mastik toolkit, written by Yuval Yarom https://cs.adelaide.edu.au/~yval/Mastik/
  ☆37Updated 5 years ago
• vusec / tlbdr
  ☆18Updated 2 years ago
• 0x5ec1ab / rowhammer_armv8
  Trigger the rowhammer bug on ARMv8
  ☆32Updated 5 years ago
• yshalabi / covert-channel-tutorial
  Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…
  ☆44Updated 5 years ago
• vusec / xlate
  Code to evaluate XLATE attacks as well existing cache attacks.
  ☆30Updated 6 years ago
• fanyao / branchspec
  Proof of concept code for the BranchSpec exploit.
  ☆9Updated 2 years ago
• heartever / primeprobe
  prime+probe code targeting a given physical address on libgcrypt run in an SGX enclave
  ☆15Updated 6 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆20Updated last month
• eepalms / gem5-newcache
  New Cache implementation using Gem5
  ☆13Updated 10 years ago
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆20Updated 4 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆59Updated 4 years ago
• flowyroll / uarchsec
  ☆44Updated 6 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• compsec-snu / specdoctor
  ☆23Updated 2 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆60Updated this week
• riscv-admin / iopmp
  Group administration repository for Tech: IOPMP Task Group
  ☆13Updated 3 months ago
• cwfletcher / stt
  ☆34Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated 5 months ago
• nagnagnet / PrimeProbe
  ☆18Updated 6 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• 0xADE1A1DE / Mastik
  ☆102Updated 2 years ago
• efeslab / dolma
  ☆12Updated 4 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago