MIRAGE (USENIX Security 2021)
☆14Nov 8, 2023Updated 2 years ago
Alternatives and similar repositories for mirage
Users that are interested in mirage are comparing it to the libraries listed below
Sorting:
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆22Feb 18, 2021Updated 5 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Aug 21, 2019Updated 6 years ago
- Code to evaluate XLATE attacks as well existing cache attacks.☆31Aug 17, 2018Updated 7 years ago
- Reload+Refresh PoC☆16Feb 26, 2020Updated 6 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆63Aug 7, 2022Updated 3 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- Collection of Spectre-type, Meltdown-type and MDS-type PoCs☆10Aug 25, 2020Updated 5 years ago
- Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.☆11Aug 8, 2019Updated 6 years ago
- ☆13Jun 22, 2019Updated 6 years ago
- New Cache implementation using Gem5☆13Apr 2, 2014Updated 11 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Jun 7, 2021Updated 4 years ago
- A flush-reload side channel attack implementation☆56Mar 26, 2022Updated 3 years ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆28Dec 18, 2025Updated 2 months ago
- ☆16Nov 28, 2024Updated last year
- The open-source component of Prime+Scope, published at CCS 2021☆37Jul 18, 2023Updated 2 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆15Mar 23, 2022Updated 3 years ago
- NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]☆19Nov 17, 2022Updated 3 years ago
- Library for Prime+Probe cache side-channel attacks on L1 and L2☆38Jun 10, 2020Updated 5 years ago
- GitHub (mirror) repository for the Mastik toolkit, written by Yuval Yarom https://cs.adelaide.edu.au/~yval/Mastik/☆42Sep 19, 2019Updated 6 years ago
- A tool for detecting Spectre vulnerabilities through fuzzing☆46Aug 25, 2021Updated 4 years ago
- ☆119Nov 14, 2022Updated 3 years ago
- ☆21Jun 17, 2022Updated 3 years ago
- Repository of the paper "Reproducing Spectre Attack with gem5, How To Do It Right?"☆18Jul 27, 2023Updated 2 years ago
- Proof of Concept of exploit against Spectre Variant 2 Vulnerability☆23May 23, 2020Updated 5 years ago
- ☆20Aug 3, 2018Updated 7 years ago
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆20Oct 13, 2022Updated 3 years ago
- ☆19Feb 18, 2021Updated 5 years ago
- Website and PoC collection for transient execution attacks☆204Mar 9, 2024Updated 2 years ago
- Notary: A Device for Secure Transaction Approval 📟☆28Feb 1, 2025Updated last year
- ☆48Dec 19, 2018Updated 7 years ago
- This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator☆46Feb 2, 2022Updated 4 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆53Jun 25, 2019Updated 6 years ago
- HW interface for memory caches☆28Apr 21, 2020Updated 5 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Apr 27, 2020Updated 5 years ago
- Tool for testing and finding minimal eviction sets☆108May 6, 2021Updated 4 years ago
- This repository contains examples of Flush+Flush cache attacks☆170Oct 12, 2021Updated 4 years ago
- ☆26Nov 16, 2023Updated 2 years ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Jun 7, 2021Updated 4 years ago
- ☆198Jun 12, 2024Updated last year