Alternatives and similar repositories for SwiftTron:

Users that are interested in SwiftTron are comparing it to the libraries listed below

• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆72Updated 3 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆22Updated last month
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆75Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆39Updated 4 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆98Updated 4 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆33Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆135Updated 5 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆43Updated 3 months ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆13Updated 3 years ago
• gl9544 / vit_transformer_fpga
  ☆13Updated last year
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆63Updated last week
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆48Updated 3 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆54Updated 2 years ago
• xliu0709 / DACSDC2021
  ☆11Updated 9 months ago
• fffasttime / AnyPackingNet
  ☆25Updated last month
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆137Updated 9 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆35Updated last year
• SamsungLabs / Butterfly_Acc
  The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …
  ☆118Updated last year
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆49Updated 3 years ago
• dldldlfma / eyeriss_v1
  ☆12Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆37Updated 3 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆20Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆46Updated this week
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆97Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆33Updated 5 months ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆94Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆125Updated this week