albertomarchisio / SwiftTron
☆28Updated last year
Related projects: ⓘ
- Open-source of MSD framework☆14Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆92Updated 5 months ago
- ☆12Updated last year
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆103Updated last year
- An FPGA Accelerator for Transformer Inference☆69Updated 2 years ago
- ☆83Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆17Updated 11 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆66Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆121Updated 4 years ago
- A co-design architecture on sparse attention☆41Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆23Updated 2 years ago
- ☆11Updated 5 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆30Updated 9 months ago
- A DNN Accelerator implemented with RTL.☆60Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆28Updated last month
- IC implementation of Systolic Array for TPU☆137Updated 6 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆10Updated 3 years ago
- Verilog implementation of Softmax function☆45Updated 2 years ago
- ☆23Updated 6 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆19Updated 3 weeks ago
- An HLS based winograd systolic CNN accelerator☆46Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆74Updated 9 months ago
- A CNN accelerator design inspired by MIT Eyeriss project☆16Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆27Updated last month
- tpu-systolic-array-weight-stationary☆17Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆28Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆32Updated 3 years ago
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆15Updated 5 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆21Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 2 years ago