abdelfattah-lab / BitMoD-HPCA-25Links
☆50Updated last month
Alternatives and similar repositories for BitMoD-HPCA-25
Users that are interested in BitMoD-HPCA-25 are comparing it to the libraries listed below
Sorting:
- ☆31Updated 2 weeks ago
- ☆48Updated 4 years ago
- A co-design architecture on sparse attention☆51Updated 4 years ago
- ☆108Updated last year
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆29Updated last year
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆14Updated 3 weeks ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆116Updated 2 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆44Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆102Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆20Updated last year
- ☆43Updated last month
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆59Updated 4 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆63Updated 6 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆90Updated 4 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆23Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆62Updated 3 weeks ago
- ☆84Updated last year
- ViTALiTy (HPCA'23) Code Repository☆23Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆17Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆90Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training☆19Updated last year
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆72Updated 6 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆33Updated last month
- ☆35Updated 5 years ago