YosysHQ / setup-oss-cad-suiteLinks
Set up your GitHub Actions workflow with a OSS CAD Suite
☆16Updated last year
Alternatives and similar repositories for setup-oss-cad-suite
Users that are interested in setup-oss-cad-suite are comparing it to the libraries listed below
Sorting:
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆21Updated this week
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- A configurable USB 2.0 device core☆31Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 3 months ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated 2 weeks ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- ☆20Updated 2 years ago
- ☆13Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- ☆41Updated 2 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- Use ECP5 JTAG port to interact with user design☆28Updated 3 years ago
- ☆45Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 2 years ago
- A Risc-V SoC for Tiny Tapeout☆17Updated 2 months ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago