Alternatives and similar repositories for setup-oss-cad-suite

Users that are interested in setup-oss-cad-suite are comparing it to the libraries listed below

• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 5 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …
  ☆13Updated last week
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆93Updated 9 months ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• lambdaconcept / lambdasoc
  ☆44Updated 4 months ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆23Updated this week
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last month
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆27Updated 4 months ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆21Updated last year
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 8 months ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 4 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆38Updated 3 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆95Updated last month
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆89Updated 6 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated last week
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆34Updated 3 years ago
• mithro / kicad-pmod
  KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specifica…
  ☆39Updated 4 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆57Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 5 months ago
• olofk / observer
  ☆41Updated 5 years ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆100Updated 2 years ago