YosysHQ / setup-oss-cad-suiteLinks
Set up your GitHub Actions workflow with a OSS CAD Suite
☆16Updated last year
Alternatives and similar repositories for setup-oss-cad-suite
Users that are interested in setup-oss-cad-suite are comparing it to the libraries listed below
Sorting:
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆24Updated this week
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆29Updated 6 months ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆16Updated last week
- USB virtual model in C++ for Verilog☆31Updated 10 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆34Updated 4 years ago
- assorted library of utility cores for amaranth HDL☆96Updated 11 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆53Updated 3 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆15Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆35Updated 4 years ago
- sample VCD files☆37Updated last month
- Use ECP5 JTAG port to interact with user design☆32Updated 4 years ago
- ☆44Updated 6 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated last month
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Nitro USB FPGA core☆87Updated last year
- Flip flop setup, hold & metastability explorer tool☆48Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last week
- Simplified environment for litex☆14Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆49Updated 3 months ago