USTC-System-Courses / CECS-LabLinks
☆40Updated last year
Alternatives and similar repositories for CECS-Lab
Users that are interested in CECS-Lab are comparing it to the libraries listed below
Sorting:
- 体系结构研讨 + ysyx高阶大纲 (WIP☆179Updated 11 months ago
- ☆156Updated last week
- ☆67Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 3 years ago
- 一生一芯的信息发布和内容网站☆132Updated last year
- Modern co-simulation framework for RISC-V CPUs☆153Updated this week
- "aura" my super-scalar O3 cpu core☆24Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Updated 2 years ago
- ☆86Updated last week
- ☆81Updated 4 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 5 months ago
- NJU Virtual Board☆289Updated last week
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆143Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆174Updated 4 years ago
- Pick your favorite language to verify your chip.☆66Updated this week
- MIT6.175 & MIT6.375 Study Notes☆42Updated 2 years ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆98Updated this week
- ☆205Updated 5 months ago
- NUDT 高级体系结构实验☆35Updated 11 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆207Updated 3 months ago
- ☆290Updated 2 weeks ago
- Build mini linux for your own RISC-V emulator!☆21Updated last year
- ☆27Updated last month
- ☆70Updated 2 years ago
- An exquisite superscalar RV32GC processor.☆160Updated 8 months ago
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆16Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆22Updated 6 months ago