usmanwardag / sobel
Implementation of Sobel Filter in Verilog
☆22Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for sobel
- ☆16Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆15Updated 8 months ago
- AXI Interconnect☆46Updated 3 years ago
- RTL code of some arbitration algorithm☆12Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated 2 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆12Updated last year
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆20Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- ☆16Updated 7 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- AXI4 BFM in Verilog☆32Updated 7 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆29Updated 6 years ago
- ☆21Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- UART design in SV and verification using UVM and SV☆37Updated 4 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- A 2D convolution hardware implementation written in Verilog☆42Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆24Updated 5 years ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 8 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Updated 4 years ago