freecores / amberLinks
Amber ARM-compatible core
☆15Updated 11 years ago
Alternatives and similar repositories for amber
Users that are interested in amber are comparing it to the libraries listed below
Sorting:
- PS2 interface☆18Updated 8 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆65Updated 2 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆34Updated 9 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 6 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- IBM PC Compatible SoC for a commercially available FPGA board☆72Updated 9 years ago
- OpenSPARC-based SoC☆74Updated 11 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆89Updated 5 years ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 7 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- Mega/Xmega soft core RTL design.☆11Updated 5 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Reverse engineering the XC2064 FPGA☆83Updated 4 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆46Updated 4 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆38Updated 3 years ago
- ZPUino HDL implementation☆90Updated 7 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆69Updated 7 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆29Updated 4 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- CMod-S6 SoC☆43Updated 7 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 5 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Tools for FPGA development.☆48Updated 4 months ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago