freecores / pid_controllerLinks
PID controller
☆24Updated 11 years ago
Alternatives and similar repositories for pid_controller
Users that are interested in pid_controller are comparing it to the libraries listed below
Sorting:
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆68Updated 4 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆91Updated 3 years ago
- An CAN bus Controller implemented in Verilog☆50Updated 10 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- USB 2.0 Device IP Core☆71Updated 8 years ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- Verilog SPI master and slave☆60Updated 9 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆81Updated last year
- MIPI DSI controller☆79Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- SPI Master Core clone from OpenCores☆11Updated 12 years ago
- UART To SPI☆18Updated 11 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆41Updated last month
- UART 16550 core☆37Updated 11 years ago
- FPGA Logic Analyzer and GUI☆143Updated 2 years ago
- A CIC filter implemented in Verilog☆23Updated 10 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆130Updated 5 years ago
- Verilog wishbone components☆121Updated last year
- DPLL for phase-locking to 1PPS signal☆32Updated 9 years ago