PID controller
☆25Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for pid_controller
Users that are interested in pid_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- ☆20Nov 7, 2019Updated 6 years ago
- Design real-time image processing, object recognition and PID control for Autonomous Drone.☆35Nov 26, 2017Updated 8 years ago
- LPC (Low Pin Count) interface peripheral module in pure Verilog☆17Jan 15, 2024Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆21Jul 17, 2014Updated 11 years ago
- Arduino style API for GD32 F1, GD32F3, GD32VF1, CH32F1, CH32V30x and STM32F1, FreeRTOS and Cmake build system included. Some rust was add…☆12Updated this week
- An embeddable FPGA SoM designed for high-speed audio and USB applications.☆26Mar 9, 2026Updated 2 weeks ago
- PID controller on an FPGA with custom RS232 addressing protocol.☆25Sep 7, 2021Updated 4 years ago
- Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.☆17Oct 7, 2025Updated 5 months ago
- FIFO implementation with different clock domains for read and write.☆14Aug 17, 2021Updated 4 years ago
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 3 years ago
- FIR filter implementation☆29Mar 19, 2020Updated 6 years ago
- Soft-microcontroller implementation of an ARM Cortex-M0☆29Apr 23, 2019Updated 6 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆18Dec 23, 2020Updated 5 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated last year
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆18Jul 9, 2024Updated last year
- Testing tools (binary/text) for RS232, QTcpSocket, QLocalSocket☆13Dec 22, 2015Updated 10 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- This tool convert qucs .sch files to kicad .sch files☆15Oct 11, 2011Updated 14 years ago
- Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) archit…☆17Jun 20, 2024Updated last year
- Hardware Assisted IEEE 1588 IP Core☆30Jul 17, 2014Updated 11 years ago
- This is STM32F429-Discovery and STM32F407 driver for OV7670, DCMI DMA SCCB Example☆16Jun 22, 2020Updated 5 years ago
- Real-time GUI display for the intensity graded FFT function using RTLSDR as an input device☆27Feb 22, 2021Updated 5 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- An ASCII Header Generator for Network Protocols☆14Dec 12, 2024Updated last year
- LiteX based FPGA gateware for Thunderscope.☆28Mar 16, 2026Updated last week
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 4 years ago
- ARM-CPU implemented verilog☆29Jan 13, 2024Updated 2 years ago
- PicoSigGen - Low cost arbitrary waveform generator☆31Aug 8, 2023Updated 2 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year