freecores / zet86
Zet - The x86 (IA-32) open implementation
☆20Updated 10 years ago
Alternatives and similar repositories for zet86:
Users that are interested in zet86 are comparing it to the libraries listed below
- PS2 interface☆17Updated 7 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆12Updated 5 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- ☆14Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- A blinky project for the ULX3S v3.0.3 FPGA board☆16Updated 6 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆16Updated 4 years ago
- Enigma in FPGA☆28Updated 5 years ago
- PCB layout for my cheap FPGA HDMI experimenting board☆10Updated 10 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆13Updated 8 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆44Updated last month
- Video Effects on VGA☆14Updated 6 years ago
- VGA-compatible text mode functionality☆16Updated 4 years ago
- XC2064 bitstream documentation☆16Updated 6 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- ☆10Updated 5 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆44Updated 2 months ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆30Updated 8 years ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12Updated 4 years ago
- IRSIM switch-level simulator for digital circuits☆31Updated 9 months ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆23Updated last year
- ☆19Updated 3 years ago
- ☆51Updated 7 years ago
- Compiler Generator Coco/R modified for VerilogEbnf☆9Updated 5 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Updated 4 years ago
- This is a higan/Verilator co-simulation example/framework☆49Updated 6 years ago
- verilog/FPGA hardware description for very simple GPU☆17Updated 5 years ago