freecores / turbo8051
turbo 8051
☆28Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for turbo8051
- USB 2.0 Device IP Core☆52Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆20Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆29Updated 4 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆61Updated 5 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- USB 1.1 Host and Function IP core☆19Updated 10 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 7 months ago
- TCP/IP controlled VPI JTAG Interface.☆59Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆57Updated 2 years ago
- I2C controller core☆33Updated last year
- Wishbone interconnect utilities☆36Updated 5 months ago
- Small (Q)SPI flash memory programmer in Verilog☆55Updated 2 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆35Updated 4 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆75Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- UART 16550 core☆30Updated 10 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆18Updated 9 years ago
- Verilog SPI master and slave☆46Updated 8 years ago
- 100 MB/s Ethernet MAC Layer Switch☆13Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆25Updated 9 years ago
- configurable cordic core in verilog☆46Updated 10 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆20Updated 6 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆75Updated 4 years ago
- ☆46Updated 2 years ago