Alternatives and similar repositories for Artix-7-PCIE-Riffa

Users that are interested in Artix-7-PCIE-Riffa are comparing it to the libraries listed below

• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆40Updated last month
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• AdriaanSwan / Verilog-I2C-Slave
  Verilog I2C Slave
  ☆24Updated 11 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆62Updated 3 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆31Updated 5 years ago
• freecores / i2c
  I2C controller core
  ☆46Updated 2 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆17Updated 2 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆49Updated 2 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆214Updated last year
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆60Updated 9 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 8 months ago
• haifengch / axi_interconnect
  ☆25Updated 3 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆25Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆45Updated 4 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆29Updated 2 years ago
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• makararasi / UVM_AXI4-Stream
  ☆14Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆46Updated 9 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• VideoGPU / MIPI_CSI2_TX
  VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
  ☆76Updated 2 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆71Updated 8 years ago
• FilMarini / FPGA_CDR_core
  FPGA implementation of a CDR targeting a Xilinx Kintex-7 for data rates up to 250 MHz
  ☆18Updated 3 years ago