ucsdsysnet / RosebudLinks
Framework for FPGA-accelerated Middlebox Development
☆45Updated 2 years ago
Alternatives and similar repositories for Rosebud
Users that are interested in Rosebud are comparing it to the libraries listed below
Sorting:
- ☆53Updated last year
- AMD OpenNIC Shell includes the HDL source files☆123Updated 7 months ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆142Updated 5 months ago
- ESnet SmartNIC hardware design repository.☆56Updated 2 weeks ago
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 7 months ago
- A Programmable Hardware Architecture for Network Transport Logic☆35Updated 3 years ago
- ☆51Updated 3 years ago
- A Fast, Scalable and Programmable Packet Scheduler in Hardware☆38Updated 6 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆103Updated 2 years ago
- ☆33Updated 9 years ago
- This repo contains the Limago code☆86Updated 3 months ago
- ☆66Updated 6 months ago
- VNx: Vitis Network Examples☆153Updated last year
- P4-14/16 Bluespec Compiler☆87Updated 7 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆21Updated 2 years ago
- Network packet parser generator☆52Updated 4 years ago
- ☆25Updated 4 years ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆279Updated 2 weeks ago
- ☆14Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆129Updated 3 years ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆131Updated 2 years ago
- AMD OpenNIC Project Overview☆276Updated 2 years ago
- ☆47Updated 5 years ago
- An Agile Chisel-Based SoC Design Framework☆27Updated 3 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆38Updated 7 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆53Updated last year
- FlowBlaze: Stateful Packet Processing in Hardware☆70Updated 2 years ago
- ☆69Updated last month