gatecat / hrt
Hot Reconfiguration Technology demo
☆39Updated 2 years ago
Alternatives and similar repositories for hrt:
Users that are interested in hrt are comparing it to the libraries listed below
- Industry standard I/O for Amaranth HDL☆28Updated 6 months ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- An FPGA reverse engineering and documentation project☆43Updated this week
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- ☆22Updated 3 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 5 months ago
- Unofficial Yosys WebAssembly packages☆70Updated this week
- Experiments with Yosys cxxrtl backend☆48Updated 3 months ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated this week
- Exploring gate level simulation☆57Updated 2 weeks ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆29Updated 8 months ago
- My pergola FPGA projects☆30Updated 3 years ago
- System on Chip toolkit for Amaranth HDL☆88Updated 6 months ago
- PicoRV☆44Updated 5 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated last week
- Awesome projects using the Amaranth HDL☆13Updated 3 months ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆40Updated this week
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 9 months ago
- 妖刀夢渡☆59Updated 6 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Board and connector definition files for nMigen☆30Updated 4 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- ☆67Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Yet Another Debug Transport☆21Updated 3 years ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆15Updated last year
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Iron: selectively turn RISC-V binaries into hardware☆23Updated last year