enjoy-digital / pcie_analyzer
PCIe analyzer experiments
☆49Updated 4 years ago
Alternatives and similar repositories for pcie_analyzer:
Users that are interested in pcie_analyzer are comparing it to the libraries listed below
- FPGA board-level debugging and reverse-engineering tool☆34Updated last year
- ☆33Updated 2 years ago
- Small footprint and configurable SPI core☆41Updated last month
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆94Updated last year
- ☆22Updated 2 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆53Updated last year
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- ☆33Updated 4 years ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆64Updated 3 years ago
- Small footprint and configurable JESD204B core☆41Updated last month
- Virtual development board for HDL design☆40Updated last year
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- Xilinx Unisim Library in Verilog☆73Updated 4 years ago
- Template project for LiteX-based SoCs☆19Updated 7 months ago
- ☆15Updated 2 years ago
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Updated 4 years ago
- Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…☆44Updated this week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 9 months ago
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- Extensible FPGA control platform☆57Updated last year
- Naive Educational RISC V processor☆78Updated 4 months ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- Open Source AES☆32Updated 10 months ago
- FPGA reference design for the the Swerv EH1 Core☆70Updated 5 years ago