lukego / easynicLinks
EasyNIC: an easy-to-use host interface for network cards
☆43Updated 7 years ago
Alternatives and similar repositories for easynic
Users that are interested in easynic are comparing it to the libraries listed below
Sorting:
- An open standard Cache Coherent Fabric Interface repository☆66Updated 5 years ago
- CoreNIC: a flexible SR-IOV SmartNIC firmware implementation supporting BPF and stateless offloads.☆97Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated last month
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- ☆64Updated 4 years ago
- P4FPGA is located at github.com/hanw/p4fpga☆12Updated 8 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- HDL tools layer for OpenEmbedded☆17Updated 8 months ago
- Network packet parser generator☆51Updated 4 years ago
- A FPGA implementation of the NTP and NTS protocols☆59Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 5 months ago
- IP submodules, formatted for easier CI integration☆29Updated last year
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆14Updated 5 years ago
- Network Development Kit (NDK) for FPGA cards with example application☆55Updated last week
- A collection of little open source FPGA hobby projects☆50Updated 5 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- chipy hdl☆17Updated 7 years ago
- SPI core☆14Updated 5 years ago
- 妖刀夢渡☆59Updated 6 years ago
- ☆16Updated last year
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆104Updated 7 years ago
- A 300 MHz to 3800 MHz RF module for the Novena Open Hardware Computing Platform☆52Updated 9 years ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆40Updated 2 months ago
- Language for composable analysis and generation of digital, analog, and RF signals☆55Updated 3 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- nextpnr portable FPGA place and route tool☆12Updated 4 years ago
- Misc open FPGA flow examples☆8Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated 2 weeks ago