Alternatives and similar repositories for zynq-ultrascale-readback-capture:

Users that are interested in zynq-ultrascale-readback-capture are comparing it to the libraries listed below

• pulp-platform / axi_llc
  ☆23Updated this week
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 8 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆43Updated 4 years ago
• pulp-platform / apb
  APB Logic
  ☆15Updated 2 months ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 7 months ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 4 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• verilator / example-systemverilog
  ☆35Updated last year
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆43Updated 3 weeks ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 4 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• slaclab / axi-pcie-core
  ☆21Updated this week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆32Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated last month
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆19Updated 3 months ago
• khoapham / bitman
  ☆24Updated 4 years ago
• merledu / TileLink
  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
  ☆20Updated 4 years ago
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆30Updated 2 years ago