stevenbell / csirxLinks
Open-source CSI-2 receiver for Xilinx UltraScale parts
☆37Updated 6 years ago
Alternatives and similar repositories for csirx
Users that are interested in csirx are comparing it to the libraries listed below
Sorting:
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated this week
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- Wishbone interconnect utilities☆43Updated this week
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Updated 6 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- ☆42Updated 5 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- ☆20Updated 3 years ago
- ☆13Updated 4 years ago
- OpenFPGA☆34Updated 7 years ago
- Adding PR to the PYNQ Overlay☆19Updated 8 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- A CIC filter implemented in Verilog☆24Updated 10 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- PicoRV☆43Updated 5 years ago