stevenbell / csirx
Open-source CSI-2 receiver for Xilinx UltraScale parts
☆37Updated 5 years ago
Alternatives and similar repositories for csirx:
Users that are interested in csirx are comparing it to the libraries listed below
- Wishbone interconnect utilities☆39Updated last month
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Extensible FPGA control platform☆59Updated last year
- Wishbone controlled I2C controllers☆47Updated 4 months ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 2 weeks ago
- USB Full Speed PHY☆42Updated 4 years ago
- ☆41Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆55Updated last week
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated last month
- Library of reusable VHDL components☆28Updated last year
- Docker Development Environment for SpinalHDL☆19Updated 7 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 11 months ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated 2 weeks ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- MIPI CSI-2 RX☆31Updated 3 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆27Updated 6 years ago
- Yosys Plugins☆21Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 2 months ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆20Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- sample VCD files☆36Updated last year