emuMonitor is a tool for "palladium" and "zebu" usage information data-collection, data-analysis and data-display.
☆16Nov 19, 2024Updated last year
Alternatives and similar repositories for emuMonitor
Users that are interested in emuMonitor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Jul 16, 2020Updated 5 years ago
- ☆15Jul 25, 2017Updated 8 years ago
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆39Jun 7, 2026Updated last week
- System on Chip verified with UVM/OSVVM/FV☆36Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- licenseMonitor is used to check instant EDA license information.☆29Aug 11, 2025Updated 10 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆20Apr 14, 2026Updated 2 months ago
- ☆22Oct 23, 2020Updated 5 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- A toop for LSF data-collection, data-analysis and information display.☆62Updated this week
- ☆23Dec 7, 2019Updated 6 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity☆39Mar 28, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Project Repo for the Simulator Independent Coverage Research☆21Feb 28, 2023Updated 3 years ago
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆12Feb 12, 2016Updated 10 years ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- A noise robust QRS delineation algorithm☆12Nov 22, 2016Updated 9 years ago
- ☆31Mar 31, 2025Updated last year
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- The experience of coding☆14Jun 16, 2017Updated 8 years ago
- ☆17Mar 17, 2022Updated 4 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆29Jul 17, 2025Updated 10 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Traffic-Sign-Reognition☆14Dec 18, 2020Updated 5 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 5 months ago
- A tool for making password-protected files☆12Jul 6, 2023Updated 2 years ago
- A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.☆12Jul 29, 2021Updated 4 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- ☆26Dec 4, 2025Updated 6 months ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆12Dec 27, 2022Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆123Apr 3, 2026Updated 2 months ago
- BEADS: Baseline Estimation And Denoising w/ Sparsity Python version☆17Nov 13, 2020Updated 5 years ago
- VIP-Bench benchmarks for evaluating secure computation frameworks (e.g., HE, MPC, SE, etc...)☆13Jun 9, 2023Updated 3 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆18Nov 11, 2025Updated 7 months ago