Alternatives and similar repositories for emuMonitor:

Users that are interested in emuMonitor are comparing it to the libraries listed below

• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆55Updated last month
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆96Updated last year
• bytedance / ic_flow_platform
  IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …
  ☆174Updated 4 months ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆62Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆24Updated last year
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆85Updated 6 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆74Updated 10 years ago
• vaughnbetz / COFFE
  ☆41Updated 7 months ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆75Updated 3 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆98Updated 4 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆70Updated 3 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆194Updated last month
• accellera / uvm
  ☆49Updated 8 years ago
• chenhaoc / cnnhwpe
  ☆65Updated 2 years ago
• pulp-platform / fpu
  ☆45Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆58Updated last year
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆31Updated 4 years ago
• RV-BOSC / OpenNoC
  ☆147Updated 3 weeks ago
• funningboy / smtdv
  make your verilog DUT test more smart
  ☆21Updated 8 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 2 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆47Updated 3 months ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆30Updated 3 weeks ago
• xupsh / ccc2021
  view at https://xupsh.github.io/ccc2021/
  ☆23Updated 3 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• liyanqing1987 / libertyParser
  liberty parser (For parsing IC timing lib file)
  ☆55Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆61Updated 2 weeks ago