Alternatives and similar repositories for PIMSYN-NN

Users that are interested in PIMSYN-NN are comparing it to the libraries listed below

• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆54Updated 4 years ago
• scalesim-project / SCALE-Sim
  Repository to host and maintain SCALE-Sim code
  ☆380Updated 3 weeks ago
• scalesim-project / scale-sim-v3
  ☆49Updated 3 months ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆81Updated 8 months ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆105Updated 7 months ago
• PSAL-POSTECH / PyTorchSim
  PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework
  ☆54Updated last week
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆20Updated 8 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆30Updated 2 years ago
• xcw-1010 / HLSPilot
  ☆45Updated 11 months ago
• wangxy-2000 / pimsim-nn
  ☆58Updated last year
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆99Updated last month
• scale-snu / attacc_simulator
  ☆112Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆163Updated this week
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆69Updated 2 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• huweim / dataflow_architecture
  Research about dataflow architecture
  ☆12Updated 2 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆70Updated 3 weeks ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆66Updated last month
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆168Updated last month
• maestro-project / maestro
  An analytical cost model evaluating DNN mappings (dataflows and tiling).
  ☆241Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆142Updated 6 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 4 months ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆11Updated 4 years ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆44Updated 5 months ago
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆48Updated last year
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆121Updated 5 years ago
• casys-kaist / NeuPIMs
  NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing
  ☆100Updated last year
• sunxt99 / PIMCOMP-NN
  ☆71Updated 9 months ago
• yhqiu16 / FDRA
  DRA+RISC-V Exploration Framework
  ☆18Updated last year