flasonil / Serial-MultiplierLinks
16 bit serial multiplier in SystemVerilog
☆12Updated 7 years ago
Alternatives and similar repositories for Serial-Multiplier
Users that are interested in Serial-Multiplier are comparing it to the libraries listed below
Sorting:
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 11 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated this week
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 7 months ago
- APB UVC ported to Verilator☆11Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆61Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Updated 2 years ago
- corundum work on vu13p☆19Updated last year
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- ☆27Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- ☆67Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- ☆64Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- BlackParrot on Zynq☆48Updated last week
- General Purpose AXI Direct Memory Access☆60Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Basic floating-point components for RISC-V processors☆10Updated 8 years ago