NetFPGA / netfpga
NetFPGA 1G infrastructure and gateware
☆371Updated 5 years ago
Alternatives and similar repositories for netfpga:
Users that are interested in netfpga are comparing it to the libraries listed below
- NetFPGA public repository☆180Updated 4 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆513Updated 4 months ago
- Example designs for FPGA Drive FMC☆232Updated last month
- Open source FPGA-based NIC and platform for in-network compute☆190Updated 9 months ago
- NetFPGA-SUME public repository☆113Updated 9 years ago
- AMD OpenNIC Project Overview☆241Updated 2 years ago
- Support for Rocket Chip on Zynq FPGAs☆403Updated 6 years ago
- OpenRISC 1200 implementation☆164Updated 9 years ago
- Connectal is a framework for software-driven hardware development.☆164Updated last year
- Small footprint and configurable PCIe core☆502Updated 2 weeks ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆568Updated 4 years ago
- Xilinx Tcl Store☆352Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆641Updated 3 months ago
- Recipe for FPGA cooking☆292Updated 4 months ago
- Verilog AXI stream components for FPGA implementation☆777Updated 6 months ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆413Updated this week
- Bus bridges and other odds and ends☆521Updated 2 weeks ago
- A simple RISC-V processor for use in FPGA designs.☆267Updated 6 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆787Updated 3 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆399Updated 3 weeks ago
- A directory of Western Digital’s RISC-V SweRV Cores☆860Updated 4 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆189Updated 6 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆124Updated 3 years ago
- The root repo for lowRISC project and FPGA demos.☆595Updated last year
- SystemRDL 2.0 language compiler front-end☆245Updated last month
- A simple, basic, formally verified UART controller☆288Updated last year
- VeeR EH1 core☆848Updated last year
- PCI express simulation framework for Cocotb☆149Updated last year
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆159Updated last year
- Verilog PCI express components☆1,211Updated 9 months ago