NetFPGA / netfpga
NetFPGA 1G infrastructure and gateware
☆365Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for netfpga
- NetFPGA public repository☆179Updated 4 years ago
- Support for Rocket Chip on Zynq FPGAs☆396Updated 5 years ago
- Example designs for FPGA Drive FMC☆221Updated last week
- Open source FPGA-based NIC and platform for in-network compute☆179Updated 6 months ago
- NetFPGA-SUME public repository☆112Updated 9 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆497Updated last month
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆624Updated last week
- Connectal is a framework for software-driven hardware development.☆161Updated last year
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆754Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆390Updated 3 weeks ago
- ☆256Updated this week
- Verilog AXI stream components for FPGA implementation☆745Updated 3 months ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆337Updated last month
- Bus bridges and other odds and ends☆490Updated 10 months ago
- Xilinx Tcl Store☆348Updated this week
- AMD OpenNIC Project Overview☆227Updated last year
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆154Updated 9 months ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆122Updated 3 years ago
- A directory of Western Digital’s RISC-V SweRV Cores☆857Updated 4 years ago
- The root repo for lowRISC project and FPGA demos.☆597Updated last year
- Recipe for FPGA cooking☆289Updated last month
- PCI express simulation framework for Cocotb☆139Updated 11 months ago
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 3 weeks ago
- Build Customized FPGA Implementations for Vivado☆294Updated this week
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆551Updated 3 years ago
- Python-based hardware modeling framework☆237Updated 5 years ago
- lowRISC Style Guides☆371Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆966Updated 4 months ago