☆15Nov 25, 2024Updated last year
Alternatives and similar repositories for RTL_Designs
Users that are interested in RTL_Designs are comparing it to the libraries listed below
Sorting:
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆34Oct 29, 2023Updated 2 years ago
- Periodica is a Beautiful yet extremely useful and intuitive Periodic Table representation.☆11Jul 20, 2022Updated 3 years ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 2 years ago
- Talabat Integration Platform API System Clone☆15Apr 7, 2025Updated 10 months ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- Magnetorquer related hardware design☆10Jan 26, 2026Updated last month
- MatLab program based on the package for ultrasound simulation Field II☆15Jan 20, 2021Updated 5 years ago
- Miscellaneous things and projects for my ZYBO and ZYNQ devices.☆11Aug 30, 2023Updated 2 years ago
- Assignment codes for CS736 Algorithms for Medical Image Processing.☆10Aug 10, 2016Updated 9 years ago
- Assume you have a large book collection in some folder/folders, and you would like to create a database of your books, so that you can kn…☆10Jan 7, 2014Updated 12 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Pocket sized Altair 8800 clone, with blinking lights.☆11Nov 26, 2021Updated 4 years ago
- Seismo-acoustic array processing routines☆11Dec 5, 2023Updated 2 years ago
- ☆11Apr 22, 2024Updated last year
- Custom ASIC Design for SHA-256☆14Nov 22, 2025Updated 3 months ago
- A simple example of using the SDAccel build flow for AWS EC2's F1 instance type. Trys to avoid magic makefiles.☆10Aug 27, 2017Updated 8 years ago
- The recipes to build the third-party libraries for MeVisLab☆15Dec 11, 2025Updated 2 months ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 10 years ago
- AVR based implementation of AUTOSAR OS☆10Nov 28, 2020Updated 5 years ago
- This code depreciated use Flextrack instead https://github.com/daveake/FlexTrack☆16Jul 17, 2017Updated 8 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- Fast MRI reconstruction on CUDA GPUs☆10Dec 30, 2023Updated 2 years ago
- An intuitive e-commerce platform that enables seamless item management and sales. Easily add products to the database and manage transact…☆11Jan 4, 2025Updated last year
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 10 years ago
- Ultrasound Project for Emboliedetection☆13Nov 10, 2015Updated 10 years ago
- CDA Telemetry Demodulator for GOES-16☆12Dec 28, 2021Updated 4 years ago
- ☆13Dec 1, 2024Updated last year
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆17Oct 4, 2022Updated 3 years ago
- This is a passion project where I aim to explore the RTL design topics of my interest.☆13May 23, 2025Updated 9 months ago
- ☆12Dec 1, 2025Updated 3 months ago
- ☆10Mar 2, 2021Updated 5 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆13Jun 9, 2021Updated 4 years ago
- Open Source iMX6 Rex module design files in Cadence. More at:☆23Aug 2, 2018Updated 7 years ago