☆15Nov 25, 2024Updated last year
Alternatives and similar repositories for RTL_Designs
Users that are interested in RTL_Designs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- Router 1x3 design and uvm verification testbach and coverage report☆12Nov 8, 2024Updated last year
- Learn and build GPU RTL from scratch☆20Aug 1, 2025Updated 7 months ago
- ☆12Mar 11, 2021Updated 5 years ago
- A simple example of using the SDAccel build flow for AWS EC2's F1 instance type. Trys to avoid magic makefiles.☆10Aug 27, 2017Updated 8 years ago
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 10 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- Maven Silicon Project☆19Oct 13, 2018Updated 7 years ago
- Custom ASIC Design for SHA-256☆14Nov 22, 2025Updated 4 months ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆106Jul 2, 2023Updated 2 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Mar 15, 2026Updated last week
- AES☆15Oct 4, 2022Updated 3 years ago
- This is a passion project where I aim to explore the RTL design topics of my interest.☆13May 23, 2025Updated 10 months ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆16Oct 4, 2022Updated 3 years ago
- Numpy-like encrypted matrix arithmetic library based on OpenFHE☆29Updated this week
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Sep 9, 2025Updated 6 months ago
- Open Processor Architecture☆26Apr 7, 2016Updated 9 years ago
- Sigma-Delta Analog to Digital Converter in FPGA (VHDL)☆15Dec 19, 2017Updated 8 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆13Jun 9, 2021Updated 4 years ago
- Periodica is a Beautiful yet extremely useful and intuitive Periodic Table representation.☆11Jul 20, 2022Updated 3 years ago
- ☆18Oct 9, 2025Updated 5 months ago
- RTL to GDS via Cadence Tools☆16May 17, 2022Updated 3 years ago
- ☆11Jul 29, 2024Updated last year
- Spectre V1 Proof-of-Concept Attack in the Rust Language☆29Apr 3, 2025Updated 11 months ago
- Automatic Test Pattern Generation using PODEM algorithm☆15May 12, 2014Updated 11 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- ☆18Jun 2, 2025Updated 9 months ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆17Oct 5, 2023Updated 2 years ago
- ☆12Mar 7, 2024Updated 2 years ago
- Verification IP project for I3C protocol☆25Feb 13, 2026Updated last month
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Jul 7, 2018Updated 7 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆16Jun 24, 2020Updated 5 years ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆28Apr 24, 2025Updated 11 months ago
- Pocket sized Altair 8800 clone, with blinking lights.☆11Nov 26, 2021Updated 4 years ago
- Assume you have a large book collection in some folder/folders, and you would like to create a database of your books, so that you can kn…☆10Jan 7, 2014Updated 12 years ago
- CDA Telemetry Demodulator for GOES-16☆12Dec 28, 2021Updated 4 years ago
- RISC-V Ibex core with Wishbone B4 interface☆20Apr 27, 2025Updated 10 months ago