Verilog Project
☆24Aug 30, 2021Updated 5 years ago
Alternatives and similar repositories for Traffic-Light-Controller-using-Verilog
Users that are interested in Traffic-Light-Controller-using-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆31Mar 5, 2021Updated 5 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- Verilog interface for HC-SR04 Ultrasonic Ranging Module☆10Aug 3, 2023Updated 3 years ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆15Feb 24, 2026Updated 8 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- All Text Books☆19Jan 9, 2023Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆133Jul 9, 2023Updated 3 years ago
- Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with…☆20Jul 21, 2025Updated last year
- Implementation of both, sequential and 5-stage pipelined x86 64-bit processor in Verilog, designed to handle data dependencies like load-…☆14Jul 11, 2023Updated 3 years ago
- A simple, working, 32-bit ALU design.☆14Dec 26, 2014Updated 11 years ago
- DMA Project using Verilog HDL☆15Dec 26, 2019Updated 6 years ago
- Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes☆11Sep 23, 2023Updated 3 years ago
- Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).☆20Aug 28, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The HDL Bits Solutions repository provides answers to the HDL Bits exercises, which are designed for practicing digital hardware design u…☆18Sep 3, 2024Updated 2 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- ☆25Nov 3, 2021Updated 4 years ago
- This repository is a summary of the RISC-V based MYTH workshop organised by VSD and Redwood EDA, made by Ahtesham Ahmed of grade 8.☆22May 12, 2025Updated last year
- ☆18Dec 13, 2022Updated 3 years ago
- DMA Hardware Description with Verilog☆20Dec 20, 2019Updated 6 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 7 years ago
- An organized and comprehensive library of resources for the RISC-V community and anyone interested in getting involved with the RISC-V ec…☆27Dec 13, 2023Updated 2 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Y86-64 processor implemented using Verilog☆17Aug 21, 2021Updated 5 years ago
- This repository is a detailed summary of RTL design using sky130 PDK organized by VLSI System Design☆28Jun 1, 2025Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆235Jan 29, 2024Updated 2 years ago
- ☆17Sep 19, 2022Updated 4 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆17Dec 8, 2020Updated 5 years ago
- ☆31Mar 22, 2026Updated 7 months ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- This project was developed using Packet Tracer version 8.2.1, showcasing a comprehensive network setup.☆22Jan 8, 2024Updated 2 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆22Apr 15, 2018Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Schematic, Layout Design & Simulation in 180nm Technology☆24Nov 21, 2020Updated 5 years ago
- The initial version of paper" OpenACM: An Open-Source SRAM-Based Approximate CiM Compiler"☆23Jul 29, 2026Updated 3 months ago
- Elana: A Simple Energy & Latency Analyzer for LLMs☆17Apr 3, 2026Updated 6 months ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- 32 bit RISC-V CPU implementation in Verilog☆36Feb 9, 2022Updated 4 years ago
- FMCW Radar verilog project☆36Jun 15, 2020Updated 6 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆160Jul 17, 2022Updated 4 years ago