☆16Mar 27, 2024Updated last year
Alternatives and similar repositories for 100daysofrtl
Users that are interested in 100daysofrtl are comparing it to the libraries listed below
Sorting:
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- ☆17Jan 13, 2024Updated 2 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆36Feb 6, 2019Updated 7 years ago
- ☆13Dec 1, 2024Updated last year
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 9 months ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆17Oct 5, 2023Updated 2 years ago
- Maven Silicon Project☆20Oct 13, 2018Updated 7 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Jun 4, 2024Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 13 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆77Oct 7, 2022Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- ☆14Oct 27, 2021Updated 4 years ago
- DDR2 memory controller written in Verilog☆82Feb 28, 2012Updated 14 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 8 months ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- ☆11Mar 12, 2024Updated last year
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- 基于玄铁openc906，搭建最小化SoC系统☆18Apr 7, 2025Updated 11 months ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 5 months ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- Source Code for 'Beginning Perl Programming' by William "Bo" Rothwell☆13Aug 1, 2019Updated 6 years ago
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated last month
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆22Sep 4, 2025Updated 6 months ago
- ☆13Feb 1, 2025Updated last year
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 7 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- ECG Classification using PyTorch☆18Jun 27, 2022Updated 3 years ago
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago