Vidhi24-hub / 100daysofrtl
☆16Updated last year
Alternatives and similar repositories for 100daysofrtl:
Users that are interested in 100daysofrtl are comparing it to the libraries listed below
- System Verilog using Functional Verification☆10Updated 11 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Architectural design of data router in verilog☆29Updated 5 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- ☆12Updated last month
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆10Updated 7 months ago
- Verilog Project☆10Updated 3 years ago
- ☆16Updated last year
- SystemVerilog examples and projects☆17Updated 6 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆16Updated 11 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆10Updated 7 months ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- ☆16Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- Maven Silicon Project☆17Updated 6 years ago
- RTL Design and Verification☆12Updated 4 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- ☆41Updated 3 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- ☆17Updated last year
- ☆19Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- Synchronous FIFO Testbench☆10Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆23Updated last year
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆87Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago