Vidhi24-hub / 100daysofrtlLinks
☆16Updated last year
Alternatives and similar repositories for 100daysofrtl
Users that are interested in 100daysofrtl are comparing it to the libraries listed below
Sorting:
- System Verilog using Functional Verification☆12Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆63Updated 2 years ago
- ☆47Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆31Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆20Updated last year
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆28Updated 6 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆95Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆63Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated 2 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆128Updated 4 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆20Updated 2 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 11 months ago
- Maven Silicon Project☆19Updated 6 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Verification IP for APB protocol☆68Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆19Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated 2 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- VIP for AXI Protocol☆142Updated 3 years ago
- ☆16Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆105Updated 7 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- SystemVerilog examples and projects☆18Updated last month
- UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.☆9Updated last year
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year