☆18Jun 12, 2023Updated 3 years ago
Alternatives and similar repositories for 100-Days-of-RTL
Users that are interested in 100-Days-of-RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆118Dec 24, 2023Updated 2 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆17Aug 13, 2023Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆131Jul 9, 2023Updated 3 years ago
- Open Source VLSI Tools☆33Feb 6, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆40Jul 23, 2023Updated 3 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- Training v0.7 results☆13Nov 18, 2025Updated 10 months ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- ☆14Aug 7, 2024Updated 2 years ago
- ☆20Sep 16, 2022Updated 4 years ago
- Custom 64-bit pipelined RISC processor☆18Dec 8, 2025Updated 9 months ago
- Providing all of my graduate school application materials + some unsolicited advice to anyone currently going through the hell that is gr…☆16Nov 1, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆16Apr 8, 2023Updated 3 years ago
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated 2 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 3 years ago
- ☆14Jul 30, 2022Updated 4 years ago
- ☆15Nov 26, 2025Updated 10 months ago
- ☆22Oct 20, 2025Updated 11 months ago
- An 8-Bit CPU implemented in an FPGA☆22Jun 8, 2020Updated 6 years ago
- ☆26Nov 11, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- All the projects and assignments done as part of VLSI course.☆21Sep 23, 2020Updated 6 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- Official website of House of Geeks ✨☆33Apr 8, 2023Updated 3 years ago
- ☆27Jun 29, 2026Updated 3 months ago
- ☆19Nov 1, 2025Updated 11 months ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- ☆21Jan 2, 2026Updated 8 months ago
- JTAG Test Access Port (TAP)☆42Jul 17, 2014Updated 12 years ago
- Website to compare Python package downloads☆45Jun 4, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆19Feb 26, 2024Updated 2 years ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆32Mar 9, 2021Updated 5 years ago
- Acceleration codes for the Ozaki-scheme on integer matrix multiplication units.☆27Dec 10, 2025Updated 9 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- ☆26Feb 26, 2024Updated 2 years ago
- ☆25Nov 4, 2023Updated 2 years ago