☆18Feb 26, 2024Updated 2 years ago
Alternatives and similar repositories for 100DaysofRTL
Users that are interested in 100DaysofRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- ☆10Oct 16, 2023Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- ☆23Feb 10, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Nov 6, 2022Updated 3 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- ☆117Dec 24, 2023Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆111Jul 9, 2023Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- ☆44Jul 20, 2023Updated 2 years ago
- Trying to get a new skill☆32Dec 31, 2024Updated last year
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆59Sep 30, 2023Updated 2 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- All design files, source code, and documentation for Project OAK, a digital watch inspired by mechanical complications.☆26Dec 14, 2025Updated 3 months ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Sep 14, 2023Updated 2 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆36Feb 6, 2019Updated 7 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated 2 years ago
- Verilog RTL Design☆47Sep 4, 2021Updated 4 years ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆14Feb 17, 2023Updated 3 years ago
- ☆37Mar 11, 2026Updated 2 weeks ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This project performs a simulation of N and P-type MOSFET transistors. Next, the creation of logic gates is performed using the simulate…☆12Oct 17, 2022Updated 3 years ago
- Online viewer of Xschem schematic files☆29Dec 14, 2025Updated 3 months ago
- My studies on context-free grammar, using ANTLR4 (C++) to generate the parser files. Some basics are developed, such as token processing…☆11Oct 17, 2022Updated 3 years ago
- Design and UVM Verification of an ALU☆11Jun 14, 2024Updated last year
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆15Sep 15, 2020Updated 5 years ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 3 months ago
- 📚 PDF reader made in Electron and Javascript, using the PDF.js library. It has automatic translation feature when selecting a text excer…☆10Oct 17, 2022Updated 3 years ago
- ☆11Jun 7, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Lightweight re-packaging of AsyncQueue library from rocket-chip☆19Jun 23, 2023Updated 2 years ago
- A Single Cycle Risc-V 32 bit CPU☆68Jan 14, 2026Updated 2 months ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- Source Code for 'Beginning Perl Programming' by William "Bo" Rothwell☆13Aug 1, 2019Updated 6 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- 100 Days of RTL☆408Aug 15, 2024Updated last year
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago