sumanth-kalluri / 128-Bit-AES-Encryption-and-Decryption-in-Verilog
This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.
☆22Updated 4 years ago
Alternatives and similar repositories for 128-Bit-AES-Encryption-and-Decryption-in-Verilog:
Users that are interested in 128-Bit-AES-Encryption-and-Decryption-in-Verilog are comparing it to the libraries listed below
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- ☆16Updated last year
- Maven Silicon Project☆17Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆21Updated 4 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆12Updated 7 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆38Updated 3 years ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆17Updated 9 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- ☆16Updated last year
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- ☆16Updated 10 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 10 months ago
- To design test bench of the APB protocol☆16Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Verification IP for APB protocol☆56Updated 4 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆11Updated last year