powerplayer9 / Voice-Based-Motor-ControlLinks
A verilog HDL based project to control a servomotor with voice commands from an android phone.
☆12Updated 5 years ago
Alternatives and similar repositories for Voice-Based-Motor-Control
Users that are interested in Voice-Based-Motor-Control are comparing it to the libraries listed below
Sorting:
- An 8 input interrupt controller written in Verilog.☆27Updated 13 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆23Updated 5 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Verilog Code for I2C Protocol☆18Updated 4 years ago
- PCI bridge☆18Updated 10 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆27Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆36Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆42Updated 7 years ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆20Updated 5 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆22Updated 7 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆13Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- System Verilog using Functional Verification☆12Updated last year
- Verilog modules required to get the OV7670 camera working☆73Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- Python Tool for UVM Testbench Generation☆53Updated last year