100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
☆40Nov 6, 2022Updated 3 years ago
Alternatives and similar repositories for 100DaysofRTL
Users that are interested in 100DaysofRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆118Jul 9, 2023Updated 2 years ago
- ☆45Jul 20, 2023Updated 2 years ago
- ☆18Feb 26, 2024Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- ☆55Jun 19, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog UVM testbench example☆38May 8, 2024Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆190Jan 29, 2024Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆52Mar 3, 2024Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆79Oct 7, 2022Updated 3 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated last month
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- Verilog program☆16Jul 27, 2020Updated 5 years ago
- ☆24Nov 4, 2023Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆141May 14, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 100 Days of RTL☆412Aug 15, 2024Updated last year
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 6 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Aug 5, 2023Updated 2 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆13Nov 26, 2024Updated last year
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- ☆21Oct 27, 2022Updated 3 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 6 months ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆28Sep 19, 2023Updated 2 years ago
- ☆10Sep 7, 2023Updated 2 years ago
- ☆10Nov 30, 2022Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆112Jul 2, 2023Updated 2 years ago
- This repository contains solutions to the practice problems available on the HDLBits platform, which cover a wide range of topics in Digi…☆12Apr 24, 2023Updated 3 years ago
- Ten Thousand Failures Blog☆12Jul 22, 2014Updated 11 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆27Aug 11, 2022Updated 3 years ago
- ☆19May 5, 2022Updated 4 years ago
- Universal Memory Interface (UMI)☆159May 13, 2026Updated last week
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆12Apr 21, 2024Updated 2 years ago
- ☆119Dec 24, 2023Updated 2 years ago
- Verilog Project☆20Aug 30, 2021Updated 4 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago