Alternatives and similar repositories for VLSI-2024

Users that are interested in VLSI-2024 are comparing it to the libraries listed below

• Manish4403 / RISC_V_with_ICACHE
  ☆13Updated 9 months ago
• Tooba12322 / RTL_Designs
  ☆14Updated 10 months ago
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆41Updated last year
• Geetima2021 / PLL-IC-design-using-Open-Source-PDK-Google-Skywater-130nm
  This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.
  ☆20Updated 3 years ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆33Updated 3 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 5 months ago
• LeiWang1999 / EthernetVideo
  Use FPGA to Transfer Image with Gigabits Ethernet
  ☆19Updated 4 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆94Updated 6 months ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 4 years ago
• mabrains / caravel_user_project_ldo
  Completed LDO Design for Skywaters 130nm
  ☆16Updated 2 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆44Updated 3 years ago
• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 5 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆66Updated 3 years ago
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 4 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆63Updated 10 months ago
• deepaktabraham / FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm
  HW and SW based implementation of Canny Edge Detection Algorithm.
  ☆12Updated 7 years ago
• devindang / dv-cpu-rv
  A harvard architecture CPU based on RISC-V.
  ☆14Updated 2 years ago
• sscs-ose / sscs-chipathon-2024
  ☆84Updated 8 months ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆15Updated 2 years ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 8 months ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆32Updated 4 years ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• srimanthtenneti / SOC-Design-ARM-M0
  This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
  ☆12Updated 2 years ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆59Updated last month
• mihir8181 / VLSI-Design-Digital-System
  This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…
  ☆32Updated 6 years ago
• vsdip / avsddac_3v3_sky130_v2
  ☆17Updated 3 years ago
• EMIL-YORKU / SensSeq
  A mixed-signal system on chip for nanopore-based DNA sequencing
  ☆34Updated 2 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆48Updated 4 years ago
• iic-jku / iic-audiodac-v1
  Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.
  ☆35Updated 3 years ago