Trying to get a new skill
☆39Dec 31, 2024Updated last year
Alternatives and similar repositories for 100-days-of-RTL
Users that are interested in 100-days-of-RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆125Jul 9, 2023Updated 3 years ago
- ☆118Dec 24, 2023Updated 2 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Verilog ADC interface for adc128s022 found in De0 Nano☆15Jul 7, 2015Updated 11 years ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 3 years ago
- I2C controller core☆53Jan 1, 2023Updated 3 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- A Pac-Man Arcade implementation for the TangNano9K using HDMI☆61Jan 26, 2025Updated last year
- LLM-Aided FPGA Design and Debug Flow☆40Aug 1, 2025Updated last year
- Simulink models of power electronics and electric motor drive circuits☆16Feb 5, 2018Updated 8 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- TFT Clock by Gowin FPGA | 华中科技大学电信学院硬件课设基于国产高云FPGA的多功能TFT屏数字钟☆10Jun 14, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 7 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆40Jul 23, 2023Updated 3 years ago
- ☆14Dec 22, 2021Updated 4 years ago
- Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024☆26Mar 20, 2025Updated last year
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 4 months ago
- 100 Days of RTL☆424Aug 15, 2024Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆119Jul 2, 2023Updated 3 years ago
- i2c fpga oled sdd1306 bresenham implementation☆16May 20, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Shramko GoPro13 Control App for multicamera 4dgs 3dgs rigs☆20Jul 31, 2026Updated 2 weeks ago
- Simulation codes for the IEEE Nework paper☆19May 27, 2025Updated last year
- Agile Hardware Design Course☆15Updated this week
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- Simulation files to be used while reading the book "Modelling and simulation of magnetics for power electronics using Python".☆17Sep 26, 2021Updated 4 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- SDSoC platforms for Digilent Zynq boards☆11Mar 2, 2017Updated 9 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Apr 20, 2018Updated 8 years ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated last year
- Design Verification Engineer interview preparation guide.☆55Jul 20, 2025Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆66Jun 7, 2026Updated 2 months ago
- Tutorial 21: Introduction to Quantum Computing: From Algorithm to Hardware☆24Sep 9, 2023Updated 2 years ago