Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI b…
☆17Aug 21, 2018Updated 8 years ago
Alternatives and similar repositories for SPI
Users that are interested in SPI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- This project is a digital design project that implements a simple programmable stepper motor controller using the Verilog hardware descri…☆10Mar 17, 2023Updated 3 years ago
- A complete UVM verification testbench for FIFO☆14Mar 21, 2016Updated 10 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Aug 26, 2021Updated 5 years ago
- Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, …☆11Nov 23, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- 为了学习UVM验证相关知识,需要动手尝试实际的项目。作为一个初学者,难以接触到实际的项目,于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中,挑选出一个简单的小设计,作为我的验证对象,并围绕它编写了UVM验证环境。☆28Oct 9, 2020Updated 6 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆56Jul 4, 2020Updated 6 years ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated 2 years ago
- ☆13Apr 24, 2022Updated 4 years ago
- UVM Verification IP to uart2bus IP.☆25Mar 7, 2022Updated 4 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- Hardware Viterbi Decoder in verilog☆31May 28, 2019Updated 7 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- few python scripts to clone all IP cores from opencores.org☆32Jan 8, 2024Updated 2 years ago
- Formulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface☆15Dec 8, 2020Updated 5 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- Verification IP for SPI protocol☆21Jul 23, 2020Updated 6 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆11May 24, 2021Updated 5 years ago
- Verification IP for AMBA APB Protocol☆35Nov 7, 2023Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆133Jul 9, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆15Dec 16, 2020Updated 5 years ago
- This is the main repository for all the examples for the book Practical UVM☆229Oct 21, 2020Updated 6 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- Motion Estimation implementation by using Verilog HDL☆14Jun 17, 2024Updated 2 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 7 years ago
- UVM interactive debug library☆34Feb 28, 2026Updated 8 months ago
- A PyTorch-based numerical simulator for decoders in quantum error correction.☆15Oct 19, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 16 bit CPU created in Vivado with Verilog☆23Jun 30, 2022Updated 4 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…