Alternatives and similar repositories for SPI:

Users that are interested in SPI are comparing it to the libraries listed below

• hanysalah / uart2bustestbench
  UVM Verification IP to uart2bus IP.
  ☆21Updated 3 years ago
• bvnirliptha / AMBA-3-AHB--LITE-Protocol-Design-and-Verification
  -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…
  ☆21Updated 9 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆42Updated 5 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆48Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆60Updated 4 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆87Updated last year
• gokulbalagopal / Verification-of-FIFO-using-SystemVerilog
  Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…
  ☆27Updated 6 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆41Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆66Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• shubhi704 / APB-Protocol
  ☆41Updated 3 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆42Updated 4 years ago
• amamory-verification / uvm-basics
  my UVM training projects
  ☆32Updated 6 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆21Updated 3 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 10 months ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆30Updated 4 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆21Updated 8 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆58Updated last year
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• freecores / apbi2c
  APB to I2C
  ☆39Updated 10 years ago
• designsolver / ahb3_uvm_tb
  AMBA 3 AHB UVM TB
  ☆32Updated 6 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆52Updated last year
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆112Updated 7 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago