pendkeomkar / SPI
Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI b…
☆18Updated 6 years ago
Alternatives and similar repositories for SPI:
Users that are interested in SPI are comparing it to the libraries listed below
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆69Updated last year
- Verification IP for I2C protocol☆41Updated 3 years ago
- UVM Verification IP to uart2bus IP.☆22Updated 3 years ago
- Verification IP for APB protocol☆62Updated 4 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆32Updated 4 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆21Updated 9 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆49Updated 4 years ago
- ☆21Updated 3 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆44Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- my UVM training projects☆32Updated 6 years ago
- ☆43Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- Synchronous FIFO Testbench☆10Updated 3 years ago
- SystemVerilog UVM testbench example☆31Updated 11 months ago
- AXI Interconnect☆47Updated 3 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆15Updated last year
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Verification IP for SPI protocol☆17Updated 4 years ago
- ☆40Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago