Abhishekvlsi / 108-RTL-ProjectsView external linksLinks
Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simple digital circuits to complex system designs. , you'll find valuable resources here to enhance your hardware design skills.
☆32Jan 18, 2025Updated last year
Alternatives and similar repositories for 108-RTL-Projects
Users that are interested in 108-RTL-Projects are comparing it to the libraries listed below
Sorting:
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆43Aug 31, 2025Updated 5 months ago
- DMA Project using Verilog HDL☆13Dec 26, 2019Updated 6 years ago
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Apr 20, 2019Updated 6 years ago
- Verilog Project☆20Aug 30, 2021Updated 4 years ago
- This repository contains solutions to the practice problems available on the HDLBits platform, which cover a wide range of topics in Digi…☆12Apr 24, 2023Updated 2 years ago
- SystemVerilog file list pruner☆16Feb 10, 2026Updated last week
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆22Sep 4, 2025Updated 5 months ago
- Summer School Week 1 & 2 repo☆11Jul 1, 2022Updated 3 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 2 years ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 4 years ago
- I2C controller core☆49Jan 1, 2023Updated 3 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 11 years ago
- UART in Verilog and VHDL☆17Aug 21, 2022Updated 3 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆20Nov 26, 2018Updated 7 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects☆28Nov 17, 2025Updated 3 months ago
- From Pytorch model to C++ for Vitis HLS☆20Updated this week
- Verilog ADC interface for adc128s022 found in De0 Nano☆14Jul 7, 2015Updated 10 years ago
- This project discusses the design procedure of a Low Dropout Voltage Regulator (LDO) circuit.☆18Feb 28, 2024Updated last year
- DMA Hardware Description with Verilog☆19Dec 20, 2019Updated 6 years ago
- RV64IMAC modelling using System Verilog HDL☆23Aug 10, 2024Updated last year
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Sep 12, 2023Updated 2 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- Official Website of Tesla NIT, Patna☆19Aug 31, 2025Updated 5 months ago
- Lab assignments for the Agile Hardware Design course☆18Nov 14, 2025Updated 3 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Jan 27, 2023Updated 3 years ago
- Find best material to prepare for Gate Electronics and Communication Engineering.☆33Feb 20, 2024Updated last year
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 9 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆109Jul 9, 2023Updated 2 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 6 years ago
- ☆53Aug 7, 2025Updated 6 months ago
- Schematic, Layout Design & Simulation in 180nm Technology☆22Nov 21, 2020Updated 5 years ago
- 100 Days of RTL☆408Aug 15, 2024Updated last year
- Single Port RAM, Dual Port RAM, FIFO☆31May 17, 2022Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 2 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Mar 6, 2025Updated 11 months ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆41Jul 11, 2025Updated 7 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆36Apr 7, 2019Updated 6 years ago