KOTHAVANI / 100-Days-of-RTL-code
☆40Updated last year
Related projects ⓘ
Alternatives and complementary repositories for 100-Days-of-RTL-code
- ☆16Updated 10 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- Architectural design of data router in verilog☆27Updated 4 years ago
- ☆99Updated 10 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- ☆10Updated last year
- ☆13Updated 8 months ago
- ☆36Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆52Updated last year
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆71Updated last year
- ☆16Updated 7 months ago
- ☆9Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆15Updated last year
- ☆16Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 5 months ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆34Updated 4 years ago
- UVM and System Verilog Manuals☆36Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆35Updated 5 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆16Updated 3 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- Verification IP for APB protocol☆56Updated 3 years ago
- opensource EDA tool flor VLSI design☆29Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆136Updated 3 months ago
- Structured UVM Course☆34Updated 10 months ago