Alternatives and similar repositories for RTL-Coding

Users that are interested in RTL-Coding are comparing it to the libraries listed below

• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆78Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆18Updated last week
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• shubhi704 / APB-Protocol
  ☆43Updated 3 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆60Updated 2 years ago
• Ummidichandrika / 100-Days-of-RTL
  ☆111Updated last year
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 9 months ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆21Updated 4 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆22Updated last year
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆19Updated last year
• Artityagi123456789 / 100DaysofRTL
  ☆17Updated last year
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆90Updated last year
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• Abhishek-Sharma182005 / 108-RTL-Projects
  Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…
  ☆13Updated 4 months ago
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• muneebullashariff / best_coding_practices
  Describes the best coding practices and guidelines
  ☆10Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆41Updated last year
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆28Updated 8 years ago
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year
• Kholoud-Ebrahim / SPI_Protocol
  UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.
  ☆9Updated last year
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆42Updated 6 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆48Updated 4 years ago
• Devipriya1921 / Traffic-Light-Controller-using-Verilog
  Verilog Project
  ☆11Updated 3 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆59Updated last year
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆9Updated 9 months ago