chsachinkumar / HDLBits-Verilog-Solutions
This repository contains solutions to the practice problems available on the HDLBits platform, which cover a wide range of topics in Digital Logic Design using Verilog HDL. The solutions have been written by me and verified to be correct using the HDLBits online tool (Icarus Verilog).
☆10Updated 2 years ago
Alternatives and similar repositories for HDLBits-Verilog-Solutions:
Users that are interested in HDLBits-Verilog-Solutions are comparing it to the libraries listed below
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆101Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆98Updated 4 years ago
- Repository for system verilog labs from cadence☆12Updated 5 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆87Updated last month
- Ethernet MAC 10/100 Mbps☆80Updated 5 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- Another tiny RISC-V implementation☆55Updated 3 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆47Updated 2 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆157Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆72Updated this week
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆41Updated 3 years ago
- Basic RISC-V Test SoC☆121Updated 6 years ago
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- RISC-V Nox core☆62Updated last month
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆153Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- ☆25Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- This repository is created for conducting RISC-V 5-day workshops☆22Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago